ADM1041A datasheet(28/56 Pages) AD

Part #	ADM1041A

Description	Secondary-Side Controller with Current Share and Housekeeping

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ADM1041A

Rev. 0 | Page 28 of 56

AC_OK

This output is true when either ACSENSE1 or ACSENSE2 is true

(configurable). It can be configured as an open-drain,

N-channel or P-channel MOSFET and as positive or negative

(inverted) logic. A pull-up or pull-down resistor is required.

This pin can be wire-OR’ed with the same pin on other

ADM1041As in the power supply. When the AC_OK pin is not

used as such, it can be configured as an analog input, MON5, or

as a voltage reference.

MON5

This is the alternative analog comparator function for the

AC_OK pin (Pin 18). The threshold is 2.5 V, and it has a

100 μA current source that allows hysteresis to be controlled by

adjusting the external source resistance. It is ideal for an OTP

sensing circuit using a thermistor as part of a voltage divider.

The OTP condition can be configured to latch off the power

supply (similar to OVP) or to allow an autorestart (soft OTP).

See Figure 22.

In Figure 22, MON2 and MON3 are configured to monitor a

negative 12 V rail. MON2 is configured as negative-going OVP,

and MON3 is configured as positive-going UVP. The 5 V power

rail is used for bias voltage.

18

10

16

7

1

MON2

VCC

+5V

–12V

MON3

THERMISTOR

MON5

Figure 22. Example of MON Pin Configuration

1.25V

1.5V

2.5V

OCP

2.5V

MON5

MON1

OVP

UVP

ACOK

ORFETOK

SHAREOK

RESET

VDDOK

VDDOV

PENOK

MON2

MON3

MON4

PSON

CLOCK

AC_OK

DC_OK

SERIAL

INTERFACE

CONFIGURE

I/Os

PWRON

CONTROL

LINES

CBD

PEN

SCL

CS

OCP

OTP/

MON5

MON1

MON2

MON3

MON4

PSON

AC_OK

DC_OK

CBD/ALERT

PEN

SDA/

PSONLINK

SCL/

AC_OKLink

ADD0

OVP

UVP

ACOK

ORFETOK

SHAREOK

VDDOV

PENOK

VDDOK

RESET

9

18

10

16

17

16

18

17

11

12

15

13

14

STATUS

(READ

REGISTERS)

CONFIGURE

(WRITE

REGISTERS)

CONTROL

REGISTERS

GENERAL

LOGIC

Figure 23. Block Diagram of Protection and General Logic

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