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ADF4193 Datasheet(PDF) 1 Page - Analog Devices

Part No. ADF4193
Description  Low Phase Noise, Fast Settling PLL Frequency Synthesizer
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

ADF4193 Datasheet(HTML) 1 Page - Analog Devices

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Low Phase Noise, Fast Settling PLL
Frequency Synthesizer
ADF4193
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
FEATURES
New, fast settling, fractional-N PLL architecture
Single PLL replaces ping-pong synthesizers
Frequency hop across GSM band in 5 μs with phase settled
by 20 μs
0.5° rms phase error at 2 GHz RF output
Digitally programmable output phase
RF input range up to 3.5 GHz
3-wire serial interface
On-chip, low noise differential amplifier
Phase noise figure of merit: −216 dBc/Hz
Loop filter design possible using ADI SimPLL
APPLICATIONS
GSM/EDGE base stations
PHS base stations
Instrumentation and test equipment
GENERAL DESCRIPTION
The ADF4193 frequency synthesizer can be used to implement
local oscillators in the upconversion and downconversion
sections of wireless receivers and transmitters. Its architecture
is specifically designed to meet the GSM/EDGE lock time
requirements for base stations. It consists of a low noise, digital
phase frequency detector (PFD), and a precision differential
charge pump. There is also a differential amplifier to convert
the differential charge pump output to a single-ended voltage
for the external voltage-controlled oscillator (VCO).
The Σ-Δ based fractional interpolator, working with the N
divider, allows programmable modulus fractional-N division.
Additionally, the 4-bit reference (R) counter and on-chip
frequency doubler allow selectable reference signal (REFIN)
frequencies at the PFD input. A complete phase-locked loop
(PLL) can be implemented if the synthesizer is used with an
external loop filter and a VCO. The switching architecture
ensures that the PLL settles inside the GSM time slot guard
period, removing the need for a second PLL and associated
isolation switches. This decreases cost, complexity, PCB area,
shielding, and characterization on previous ping-pong GSM
PLL architectures.
FUNCTIONAL BLOCK DIAGRAM
N COUNTER
SW1
CPOUT+
CPOUT–
SW2
REFERENCE
DATA
LE
24-BIT
DATA
REGISTER
CLK
REFIN
AGND1
AGND2
DGND1
DGND2
DGND3
SDGND
SWGND
VDD
DGND
LOCK DETECT
RDIV
NDIV
SDVDD DVDD1 DVDD2 DVDD3 AVDD1
VP1
VP2
VP3RSET
OUTPUT
MUX
MUXOUT
+
HIGH Z
PHASE
FREQUENCY
DETECTOR
ADF4193
FRACTIONAL
INTERPOLATOR
MODULUS
REG
FRACTION
REG
INTEGER
REG
RFIN+
RFIN–
×2
DOUBLER
4-BIT R
COUNTER
/2
DIVIDER
CHARGE
PUMP –
+
+
DIFFERENTIAL
AMPLIFIER
CMR
AIN–
AIN+
AOUT
SW3
Figure 1.


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