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MP8830 Datasheet(PDF) 6 Page - Exar Corporation |
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MP8830 Datasheet(HTML) 6 Page - Exar Corporation |
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6 / 20 page  MP8830 6 Rev. 1.00 Parameter Test Conditions/Comments Units Max Typ Min Symbol 3-State Leakage IOZ –10 10 µA In pass-through mode Digital Timing Specifications2 For testing, rise time = fall time = 10 ns. Output loading = 60 pF except for AD0-AD9 for which loading is 40 pF. Rise and fall times faster than 5 ns should be avoided. AENL, BENL, CENL Pulse Width t1 125 ns D/A Data Hold Time t2 20 ns BENL Rising Edge to CENL Rising Edge t3 270 ns AENL Rising Edge to CVL Falling Edge t4 30 ns D/A Data Setup Time t5 20 ns Analog Input Hold Time t6 20 ns Measured as part of analog feedthrough test. Note, ttapmax < t4min + t6min. CVL Rising Edge to AENL Rising Edge t7 230 ns A/D Data Enable Time t8 40 ns CVL to Channel A data. BENL to Channel B data. CENL to Channel C data. CENL Rising Edge to CVL Rising Edge t9 40 ns Analog Input Settled to 0.1% t10 50 ns Assumes the sample is taken at the rising edge of AENL. A/D Data Hold Time t11 20 ns Aperture Delay tAP 20 40 ns Analog sampling window delay from CVL ris- ing ( ↑) edge (start) or AENL rising (↑) edge (end). CVL Falling Edge to BENL Rising Edge t12 180 ns Delay from CD5-14 to AD0-9 with CREN=1 t13 50 ns Delay from AD0-9 to CD5-14 with CREN = 1 t14 50 ns Delay from DCL Falling Edge to Clamp on. t15 40 ns External analog clamp voltage settling de- pends on external circuitry. Delay from DCL Rising Edge to Clamp off. t16 40 ns External analog clamp voltage settling de- pends on external circuitry. Time for AD0-9 and CD5-14 to switch from normal operation to pass through mode or vise versa (i.e. bus contention). t17 0 40 ns User should stop driving the bus before changing the mode and data will not be valid for 40 ns after a change of mode. Digital Quiet Time t18 15 ns This quiet time is necessary to reduce digital crosstalk during the critical sampling time. The accuracy of each conversion may be cor- rupted due to digital noise on the board during this period. Digital Quiet Time t19 40 ns This quiet time is necessary to reduce digital crosstalk during the critical sampling time. The accuracy of each conversion may be cor- rupted due to digital noise on the board during this period. Notes 1 Production testing performanced at 25 °C. 2 Not production tested. |
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