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TAS5132DDVRG4 Datasheet(PDF) 3 Page - Texas Instruments

Part # TAS5132DDVRG4
Description  STEREO DIGITAL AMPLIFIER POWER STAGE
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TAS5132DDVRG4 Datasheet(HTML) 3 Page - Texas Instruments

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MODE Selection Pins
Package Heat Dissipation Ratings
(1)
TAS5132
SLES190 – DECEMBER 2006
GENERAL INFORMATION (continued)
MODE PINS
PWM INPUT
OUTPUT CONFIGURATION
PROTECTION SCHEME
M3
M2
M1
0
0
0
2N (1) AD/BD modulation
2 channels BTL output
BTL mode (2)
0
0
1
Reserved
0
1
0
1N (1) AD modulation
2 channels BTL output
BTL mode (2)
0
1
1
1N (1) AD modulation
1 channel PBTL output
PBTL mode. Only PWM_A input is used.
Protection works similarly to BTL mode (2). Only
difference in SE mode is that OUT_X is Hi-Z
1
0
0
1N (1) AD modulation
4 channels SE output
instead of a pulldown through internal pulldown
resistor.
1
0
1
Protection system work similarly to BTL mode
(2) (0, 0, 0); however the PWM input protection
2N (1) AD/BD modulation
2 channels BTL output
is disabled. Also, overcurrent detection will be
more sensitive and will latch if an error occurs.
1
1
0
Reserved
1
1
1
(1)
The 1N and 2N naming convention is used to indicate the required number of PWM lines to the power stage per channel in a specific
mode.
(2)
An overload protection (OLP) occurring on A or B causes both channels to shut down. An OLP on C or D works similarly. Global errors
like overtemperature error (OTE), undervoltage protection (UVP), and power-on reset (POR) affect all channels.
PARAMETER
TAS5132DDV
RθJC (°C/W)—2 BTL or 4 SE channels (8 transistors)
1.4
RθJC (°C/W)—1 BTL or 2 SE channel(s) (4 transistors)
2.6
RθJC (°C/W)—(1 transistor)
8.7
Pad area(2)
15 mm2
(1)
JC is junction-to-case, CH is case-to-heatsink.
(2)
RθCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The
RθCH with this condition is 2.5°C/W for the DDV package.
3
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