8

Integrated Circuit Solution Inc.

LPSR025-0A 6/7/2002

IC62LV12816DL

IC62LV12816DLL

-55

-70

-100

Symbol Parameter

Min.

Max.

Min.

Max.

Min.

Max

Unit

Write Cycle Time

55

—

70

—

100

—

ns

CE1 Low and CE2 HIGH to Write End

50

—

65

—

80

—

ns

Address Setup Time to Write End

50

—

65

—

80

—

ns

Address Hold from Write End

0

—

0

—

0

—

ns

Address Setup Time

0

—

0

—

0

—

ns

LB, UB Valid to End of Write

45

—

60

—

80

—

ns

WE Pulse Width

45

—

40

—

80

—

ns

Data Setup to Write End

25

—

30

—

40

—

ns

Data Hold from Write End

0

—

0

—

0

—

ns

—

30

—

30

—

40

ns

5

—

5

—

5

—

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V

and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of CE1 LOW, and

UB or LB, WE LOW, and CE2 HIGH. All signals must be in

valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are

referenced to the rising or falling edge of the signal that terminates the Write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

DATA UNDEFINED

VALID ADDRESS

HIGH-Z

ADDRESS

CE1

UB, LB

WE

CE2

AC WAVEFORMS

Notes:

1. WRITE is an internally generated signal asserted during an overlap of the

and

UB inputs being in the LOW state.