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PDM41028
Rev. 2.2 - 4/29/98
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Read Cycle No. 1(4, 5)
Read Cycle No. 2(2, 4, 6)
AC Electrical Characteristics
SHADED AREA = PRELIMINARY DATA
Notes referenced are after Data Retention Table.
Description
-10(7)
-12(7)
-15
READ Cycle
Sym
Min. Max. Min. Max. Min. Max. Units
READ cycle time
tRC
10
12
15
ns
Address access time
tAA
10
12
15
ns
Chip enable access time
tACE
10
12
15
ns
Output hold from address change
tOH
3
33
ns
Chip enable to output in low Z(1,3)
tLZCE
5
55
ns
Chip disable to output in high Z(1,2,3)
tHZCE
667
ns
Chip enable to power up time(3)
tPU
0
00
ns
Chip disable to power down time(3)
tPD
10
12
15
ns
Output enable access time
tAOE
666
ns
Output enable to output in low Z (1,3)
tLZOE
0
00
ns
Output disable to output in high Z(1,3)
tHZOE
666
ns
tRC
tAA
tOH
PREVIOUS DATA VALID
DOUT
ADDR
DATA VALID
tRC
tACE
tAA
tLZCE
tHZCE
tLZOE
tHZOE
tAOE
ADDR
CE
OE
DOUT
DATA VALID