AD7674 datasheet(17/28 Pages) AD | 18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC

Part No.	AD7674

Description	18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC

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Manufacturer	AD [Analog Devices]

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AD7674

Transfer Functions

Except in 18-bit interface mode, the AD7674 offers straight

binary and twos complement output coding when using OB/2C.

See Figure 26 and Table 8 for the ideal transfer characteristic.

000...000

000...001

000...010

111...101

111...110

111...111

ANALOG INPUT

+FS – 1.5 LSB

+FS – 1 LSB

–FS + 1 LSB

–FS

–FS + 0.5 LSB

03083-0-026

Figure 26. ADC Ideal Transfer Function

Table 8. Output Codes and Ideal Input Voltages

Description

Analog Input

VREF = 4.096 V

Straight

Binary

(Hex)

Twos

Complement

(Hex)

FSR – 1 LSB

4.095962 V

3FFFF1

1FFFF1

FSR – 2 LSB

4.095924 V

3FFFE

1FFFE

Midscale + 1 LSB

31.25 µV

20001

00001

Midscale

0 V

20000

00000

Midscale – 1 LSB

–31.25 µV

1FFFF

3FFFF

–FSR + 1 LSB

–4.095962 V

00001

20001

–FSR

–4.096 V

000002

200002

1 This is also the code for overrange analog input (VIN+ – VIN–

above VREF – VREFGND).

2 This is also the code for underrange analog input (VIN+ – VIN–

below –VREF + VREFGND).

AVDD

AGND

DGND

DVDD

OVDD

OGND

CNVST

BUSY

SDOUT

SCLK

RD

CS

RESET

PD

2.5V REF

NOTE 1

REFBUFIN

20

Ω

D

CLOCK

AD7674

µC/µP/DSP

SERIAL PORT

DIGITAL SUPPLY

(3.3V OR 5V)

ANALOG

SUPPLY

(5V)

DVDD

OB/2C

NOTE 6

PDBUF

DVDD

50k

Ω

100nF

1M

Ω

IN+

ANALOG INPUT+

CC

2.7nF

U1

NOTE 3

NOTE 4

50

Ω

AD8021

–

+

15

Ω

NOTE 2

NOTE 5

ADR421

10

µF

100nF

+

10

µ F

100nF

+

100nF

+

10

µ F

IN–

ANALOG INPUT–

CC

2.7nF

U2

NOTE 3

NOTE 4

50

Ω

AD8021

–

+

15

Ω

50

Ω

100nF

NOTES

1. SEE VOLTAGE REFERENCE INPUT SECTION.

2. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION.

3.THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.

4. SEE ANALOG INPUTS SECTION.

5. OPTION, SEE POWER SUPPLY SECTION.

6. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.

47

µF

MODE1

MODE0

NOTE 1

CREF

REF

REFGND

03083-0-027

Figure 27. Typical Connection Diagram (Internal Reference Buffer, Serial Interface)

Rev. 0 | Page 17 of 28

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