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AD7674 Datasheet(PDF) 16 Page - Analog Devices |
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AD7674 Datasheet(HTML) 16 Page - Analog Devices |
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16 / 28 page  AD7674 Rev. 0 | Page 16 of 28 CIRCUIT INFORMATION IN+ REF REFGND IN– MSB 4C 2C C C LSB SW+ SWITCHES CONTROL 262,144C 131,072C MSB 4C 2C C C LSB SW– BUSY OUTPUT CODE CNVST CONTROL LOGIC COMP 262,144C 131,072C 03083–0–025 Figure 25. ADC Simplified Schematic The AD7674 is a very fast, low power, single-supply, precise 18-bit analog-to-digital converter (ADC) using successive approximation architecture. The AD7674’s linearity and dynamic range are similar to or better than many Σ-∆ ADCs. With the advantages of its successive architecture, which ease multiplexing and reduce power with throughput, it can be advantageous in applications that normally use Σ-∆ ADCs. The AD7674 features different modes to optimize performance according to the applications. In Warp mode, the AD7674 is capable of converting 800,000 samples per second (800 kSPS). The AD7674 provides the user with an on-chip track/hold, successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7674 can be operated from a single 5 V supply and can be interfaced to either 5 V or 3 V digital logic. It is housed in a 48-lead LQFP, or a tiny 48-lead LFCSP package that offers space savings and allows for flexible configurations as either a serial or parallel interface. The AD7674 is a pin-to-pin compatible upgrade of the AD7676, AD7678, and AD7679. CONVERTER OPERATION The AD7674 is a successive approximation ADC based on a charge redistribution DAC. Figure 25 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 18 binary weighted capacitors that are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the comparator’s input are connected to AGND via SW+ and SW–. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN– inputs. When the acquisition phase is complete and the CNVST input goes low, a conversion phase is initiated. When the conversion phase begins, SW+ and SW– are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between the IN+ and IN– inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4, ... VREF/262144). The control logic toggles these switches, starting with the MSB first, to bring the comparator back into a balanced condition. After completing this process, the control logic generates the ADC output code and brings the BUSY output low. Modes of Operation The AD7674 features three modes of operation: Warp, Normal, and Impulse. Each mode is more suited for specific applications. Warp mode allows conversion rates up to 800 kSPS. However, in this mode and this mode only, the full specified accuracy is guaranteed only when the time between conversions does not exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms (e.g., after power-up), the first conversion result should be ignored. This mode makes the AD7674 ideal for applications where a fast sample rate is required. Normal mode is the fastest mode (666 kSPS) without any limitation on the time between conversions. This mode makes the AD7674 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. Impulse mode, the lowest power dissipation mode, allows power saving between conversions. The maximum throughput in this mode is 570 kSPS. When operating at 1 kSPS, for example, it typically consumes only 136 µW. This feature makes the AD7674 ideal for battery-powered applications. |
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