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AD7674 Datasheet(PDF) 5 Page - Analog Devices

Part No. AD7674
Description  18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7674 Datasheet(HTML) 5 Page - Analog Devices

 
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AD7674
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figure 34 and Figure 35
Convert Pulsewidth
t1
10
ns
Time between Conversions (Warp Mode/Normal Mode/Impulse Mode)1
t2
1.25/1.5/1.75
µs
CNVST LOW to BUSY HIGH Delay
t3
35
ns
BUSY HIGH All Modes Except Master Serial Read after Convert
(Warp Mode/Normal Mode/Impulse Mode)
t4
1/1.25/1.5
µs
Aperture Delay
t5
2
ns
End of Conversion to BUSY LOW Delay
t6
10
ns
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
t7
1/1.25/1.5
µs
Acquisition Time
t8
250
ns
RESET Pulsewidth
t9
10
ns
Refer to Figure 36, Figure 37, and Figure 38 (Parallel Interface Modes)
CNVST LOW to Data Valid Delay (Warp Mode/Normal Mode/Impulse Mode)
t10
1/1.25/1.5
µs
Data Valid to BUSY LOW Delay
t11
20
ns
Bus Access Request to Data Valid
t12
45
ns
Bus Relinquish Time
t13
5
15
ns
Refer to Figure 40 and Figure 41 (Master Serial Interface Modes) 2
CS LOW to SYNC Valid Delay
t14
10
ns
CS LOW to Internal SCLK Valid Delay
t15
10
ns
CS LOW to SDOUT Delay
t16
10
ns
CNVST LOW to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode)
t17
25/275/525
ns
SYNC Asserted to SCLK First Edge Delay3
t18
3
ns
Internal SCLK Period3
t19
25
40
ns
Internal SCLK HIGH3
t20
12
ns
Internal SCLK LOW3
t21
7
ns
SDOUT Valid Setup Time3
t22
4
ns
SDOUT Valid Hold Time3
t23
2
ns
SCLK Last Edge to SYNC Delay3
t24
3
CS HIGH to SYNC HI-Z
t25
10
ns
CS HIGH to Internal SCLK HI-Z
t26
10
ns
CS HIGH to SDOUT HI-Z
t27
10
ns
BUSY HIGH in Master Serial Read after Convert3
t28
Table 4
CNVST LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode/Impulse Mode)
t29
1/1.25/1.5
µs
SYNC Deasserted to BUSY LOW Delay
t30
25
ns
Refer to Figure 42 and Figure 43 (Slave Serial Interface Modes)
External SCLK Setup Time
t31
5
ns
External SCLK Active Edge to SDOUT Delay
t32
3
18
ns
SDIN Setup Time
t33
5
ns
SDIN Hold Time
t34
5
ns
External SCLK Period
t35
25
ns
External SCLK HIGH
t36
10
ns
External SCLK LOW
t37
10
ns
1In Warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3In Serial Master Read during Convert mode. See
for Serial Master Read after Convert mode.
Table 4
Rev. 0 | Page 5 of 28


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