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ADN2804 Datasheet(PDF) 23 Page - Analog Devices

Part No. ADN2804
Description  622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADN2804 Datasheet(HTML) 23 Page - Analog Devices

 
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ADN2804
Rev. 0 | Page 23 of 24
50Ω
50Ω
PIN
VREF
NIN
CIN
COUT
COUT
V1
CIN
V1b
V2
V2b
LIMAMP
CDR
+
DATAOUTP
DATAOUTN
1
V1
V1b
V2
V2b
VDIFF
23
4
VREF
VTH
ADN2804
VDIFF = V2–V2b
VTH = ADN2804 QUANTIZER THRESHOLD
NOTES:
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE
VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO
THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES,
EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER
DOES NOT RECOGNIZE THIS AS A VALID STATE.
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2804. THE
QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.
TIA
VCC
Figure 26. Example of Baseline Wander
DC-COUPLED APPLICATION
The inputs to the ADN2804 can also be dc-coupled. This may
be necessary in burst mode applications, where there are long
periods of CIDs, and baseline wander cannot be tolerated. If the
inputs to the ADN2804 are dc-coupled, care must be taken not
to violate the input range and common-mode level require-
ments of the ADN2804 (see Figure 27 through Figure 29). If dc
coupling is required and the output levels of the TIA do not
adhere to the levels shown in Figure 28, level shifting must be
performed and/or an attenuator must be placed between the
TIA outputs and the ADN2804 inputs.
0.1µF
NIN
PIN
ADN2804
2.5V
VREF
TIA
VCC
50Ω
50Ω
50Ω
50Ω
3kΩ
Figure 27. DC-Coupled Application
PIN
V p-p = PIN – NIN = 2
× VSE = 10mV AT SENSITIVITY
VSE = 5mV MIN
VCM = 2.3V MIN
(DC-COUPLED)
NIN
Figure 28. Minimum Allowed DC-Coupled Input Levels
PIN
V p-p = PIN – NIN = 2
× VSE = 2.0V MAX
VSE = 1.0V MAX
VCM = 2.3V
(DC-COUPLED)
NIN
Figure 29. Maximum Allowed DC-Coupled Input Levels


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