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ADN2804 Datasheet(PDF) 19 Page - Analog Devices

Part No. ADN2804
Description  622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADN2804 Datasheet(HTML) 19 Page - Analog Devices

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ADN2804
Rev. 0 | Page 19 of 24
REFERENCE CLOCK (OPTIONAL)
A reference clock is not required to perform clock and data
recovery with the ADN2804; however, support for an optional
reference clock is provided. The reference clock can be driven
differentially or in a single-ended fashion. If the reference
clock is not being used, REFCLKP should be tied to VCC, and
REFCLKN can be left floating or tied to VEE (the inputs are
internally terminated to VCC/2). See Figure 21 through Figure
23 for sample configurations.
The REFCLK input buffer accepts any differential signal with a
peak-to-peak differential amplitude of greater than 100 mV (for
example, LVPECL or LVDS) or a standard single-ended, low
voltage TTL input, providing maximum system flexibility.
Phase noise and duty cycle of the reference clock are not
critical, and 100 ppm accuracy is sufficient.
100kΩ
VCC/2
100kΩ
ADN2804
REFCLKP
10
11
REFCLKN
BUFFER
Figure 21. Differential REFCLK Configuration
100kΩ
VCC/2
100kΩ
ADN2804
REFCLKP
OUT
REFCLKN
BUFFER
VCC
CLK
OSC
Figure 22. Single-Ended REFCLK Configuration
100kΩ
VCC/2
100kΩ
ADN2804
REFCLKP
10
11
NC
REFCLKN
BUFFER
VCC
Figure 23. No REFCLK Configuration
There are two mutually exclusive uses, or modes, of the
reference clock. The reference clock can be used either to help
the ADN2804 lock onto data or to measure the frequency of the
incoming data to within 0.01%. The modes are mutually
exclusive because in the first use the user knows exactly what
the data rate is and wants to force the part to lock onto only that
data rate, and in the second use the user does not know what
the data rate is and wants to measure it.
Lock-to-reference mode is enabled by writing a 1 to I2C Register
Bit CTRLA[0]. Fine data rate readback mode is enabled by
writing a 1 to I2C Register Bit CTRLA[1]. Writing a 1 to both of
these bits at the same time causes an indeterminate state and is
not supported.
Using the Reference Clock to Lock onto Data
In this mode, the ADN2804 locks onto a frequency derived
from the reference clock according to
Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7, 6]
The user must provide a reference clock that is a function of the
data rate. By default, the ADN2804 expects a reference clock of
19.44 MHz. Other options are 38.88 MHz, 77.76 MHz, and
155.52 MHz, which are selected by programming CTRLA[7, 6].
CTRLA[5:2] should be programmed to [0101] for all cases.
Table 11. CTRLA Settings
CTRLA[7, 6]
Range (MHz)
CTRLA[5:2]
Ratio
00
19.44
0101
25
01
38.88
0101
25
10
77.76
0101
25
11
155.52
0101
25
For example, if the reference clock frequency is 38.88 MHz and the
input data rate is 622.08 Mbps, CTRLA[7, 6] is set to [01] to
produce a divided-down reference clock of 19.44 MHz, and
CTRLA[5:2] is set to [0101], that is, 5, because
622.08 Mbps/19.44 MHz = 25
In this mode, if the ADN2804 loses lock for any reason, it relocks
onto the reference clock and continues to output a stable clock.
While the ADN2804 is operating in lock-to-reference mode,
a 0 to 1 transition should be written into the CTRLA[0] bit to
initiate a lock-to-reference clock command.


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