Electronic Components Datasheet Search
  English  ▼

Delete All


Preview PDF Download HTML

ADN2804 Datasheet(PDF) 15 Page - Analog Devices

Part No. ADN2804
Description  622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier
Download  24 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AD [Analog Devices]
Homepage  http://www.analog.com

ADN2804 Datasheet(HTML) 15 Page - Analog Devices

Zoom Inzoom in Zoom Outzoom out
 15 / 24 page
background image
Rev. 0 | Page 15 of 24
At medium jitter frequencies, the gain and tuning range of the
VCO are not large enough to track input jitter. In this case, the
VCO control voltage becomes large and saturates, and the VCO
frequency dwells at one extreme of its tuning range. The size of
the VCO tuning range, therefore, has only a small effect on the
jitter accommodation. The delay-locked loop control voltage is
now larger; therefore, the phase shifter takes on the burden of
tracking the input jitter. The phase shifter range, in UI, can be
seen as a broad plateau on the jitter tolerance curve. The phase
shifter has a minimum range of 2 UI at all data rates.
The gain of the loop integrator is small for high jitter
frequencies; therefore, larger phase differences are needed to
increase the loop control voltage enough to tune the range of
the phase shifter. However, large phase errors at high jitter
frequencies cannot be tolerated. In this region, the gain of the
integrator determines the jitter accommodation. Because the
gain of the loop integrator declines linearly with frequency,
jitter accommodation is lower with higher jitter frequency. At
the highest frequencies, the loop gain is very small, and little
tuning of the phase shifter can be expected. In this case, jitter
accommodation is determined by the eye opening of the input
data, the static phase error, and the residual loop jitter generation.
The jitter accommodation is roughly 0.5 UI in this region. The
corner frequency between the declining slope and the flat region
is the closed-loop bandwidth of the delay-locked loop, which is
roughly 1.0 MHz at 622 Mbps.

Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24 

Datasheet Download

Link URL

Privacy Policy
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com

Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn