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ADN2804 Datasheet(PDF) 10 Page - Analog Devices

Part No. ADN2804
Description  622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier
Download  24 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADN2804 Datasheet(HTML) 10 Page - Analog Devices

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ADN2804
Rev. 0 | Page 10 of 24
I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
1
A5
00000
X
MSB = 1 SET BY
PIN 19
0 = WR
1 = RD
SLAVE ADDRESS [6...0]
R/W
CTRL.
Figure 7. Slave Address Configuration
S SLAVE ADDR, LSB = 0 (WR) A(S)
A(S)
A(S)
DATA
SUB ADDR
A(S) P
DATA
Figure 8. I2C Write Data Transfer
S
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(M) = LACK OF ACKNOWLEDGE BY MASTER
S
SLAVE ADDR, LSB = 0 (WR)
SLAVE ADDR, LSB = 1 (RD)
A(S)
A(S)
SUB ADDR
A(S) DATA A(M)
DATA
P
A(M)
Figure 9. I2C Read Data Transfer
START BIT
S
STOP BIT
P
ACK
ACK
WR
ACK
D0
D7
A0
A7
A5
A6
SLADDR[4...0]
SLAVE ADDRESS
SUB ADDRESS
DATA
SUB ADDR[6...1]
DATA[6...1]
SCK
SDA
Figure 10. I2C Data Transfer Timing
tBUF
SDA
SS
SCK
tF
tLOW
tR
tF
tHD;STA
tHD;DAT
tSU;DAT
tHIGH
tSU;STA
tSU;STO
tHD;STA
tR
P
S
Figure 11. I2C Port Timing Diagram


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