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CY7C006 Datasheet(PDF) 6 Page - Cypress Semiconductor

Part No. CY7C006
Description  16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C006 Datasheet(HTML) 6 Page - Cypress Semiconductor

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CY7C006
CY7C016
6
Switching Characteristics Over the Operating Range[7]
7C006-15
7C016-15
7C006-25
7C016-25
7C006-35
7C016-35
7C006-55
7C016-55
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
25
35
55
ns
tAA
Address to Data Valid
15
25
35
55
ns
tOHA
Output Hold From Address Change
3
3
3
3
ns
tACE
CE LOW to Data Valid
15
25
35
55
ns
tDOE
OE LOW to Data Valid
10
13
20
25
ns
tLZOE
[8, 9, 10]
OE Low to Low Z
3
3
3
3
ns
tHZOE
[8, 9, 10]
OE HIGH to High Z
10
15
15
25
ns
tLZCE
[8, 9, 10]
CE LOW to Low Z
3
3
3
3
ns
tHZCE
[8, 9, 10]
CE HIGH to High Z
10
15
15
25
ns
tPU
[10]
CE LOW to Power-Up
0
0
0
0
ns
tPD
[10]
CE HIGH to Power-Down
15
25
35
55
ns
WRITE CYCLE
tWC
Write Cycle Time
15
25
35
55
ns
tSCE
CE LOW to Write End
12
20
30
45
ns
tAW
Address Set-Up to Write End
12
20
30
45
ns
tHA
Address Hold From Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tPWE
Write Pulse Width
12
20
25
40
ns
tSD
Data Set-Up to Write End
10
15
15
25
ns
tHD
[11]
Data Hold From Write End
0
0
0
0
ns
tHZWE
[9, 10]
R/W LOW to High Z
10
15
20
25
ns
tLZWE
[9, 10]
R/W HIGH to Low Z
3
3
3
3
ns
tWDD
[12]
Write Pulse to Data Delay
30
50
60
80
ns
tDDD
[12]
Write Data Valid to Read Data Valid
25
30
35
60
ns
BUSY TIMING[13]
tBLA
BUSY LOW from Address Match
15
20
20
30
ns
tBHA
BUSY HIGH from Address Mismatch
15
20
20
30
ns
tBLC
BUSY LOW from CE LOW
15
20
20
30
ns
tBHC
BUSY HIGH from CE HIGH
15
17
25
30
ns
tPS
Port Set-Up for Priority
5
5
5
5
ns
tWB
R/W LOW after BUSY LOW
0
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH
13
17
25
30
ns
tBDD
[14]
BUSY HIGH to Data Valid
Note 13
Note 13
Note 13
Note 13
ns
Notes:
7.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
8.
At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
9.
Test conditions used are Load 3.
10. This parameter is guaranteed but not tested.
11. Must be met by the device writing to the RAM under all operating conditions.
12. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
13. Test conditions used are Load 2.
14. tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual).


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