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CE71J4 Datasheet(PDF) 2 Page - Fujitsu Component Limited. |
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CE71J4 Datasheet(HTML) 2 Page - Fujitsu Component Limited. |
2 / 4 page L-Series with 44µm Inline Pad Pitch and Au Bump Frame Total Gates Total Pads Signals CE71L4 356K 304 264 CE71L5 476K 352 304 CE71L6 677K 420 360 CE71L7 1,034K 520 428 CE71L8 1,469K 620 504 CE71L9 1,976K 720 504 CE71LA 2,513K 812 504 CE71LB 3,001K 888 504 CE71LC 3,506K 960 504 CE71LD 4,050K 1,032 504 CE71LE 5,043K 1,152 504 T-Series with 88µm Inline Pad Pitch and Wire Bonding Frame Total Gates Total Pads Signals CE71T2 347K 144 128 CE71T3 524K 176 156 CE71T4 734K 208 178 CE71T5 845K 224 192 CE71T6 963K 240 206 CE71T7 1.110K 256 220 CE71T8 1.407K 288 248 CE71T9 1.559K 304 264 CE71TA 1.827K 328 264 CE71TB 2.088K 352 312 CE71TC 2.398K 376 312 CE71TD 3.040K 424 360 CE71TE 3.645K 464 360 CE71TG 5.152K 552 264 Mixed-Signal Macros D/A Converters • 10-bit: 1 MS/s, 1.5 MS/s, 30 MS/s, 50 MS/s, 100 MS/s, 220 MS/s • 8-bit: 200 KS/s, 1 MS/s, 50 MS/s A/D Converters • 12-bit: 1 MS/s • 10-bit: 1 MS/s, 20 MS/s, 40 MS/s • 8-bit: 1 MS/s, 30 MS/s, 50 MS/s • 6-bit: 100 MS/s, 500 MS/s Multiplier Compiler • Multiplicand (m): 4 ≤ m ≤ 32 • Multiplier (n): 4 ≤ n ≤ 32 (even number only) Memory Macros • SRAM Compiler: single and dual port (1 R/W, 1R), up to 72K bits per block, both BUS and Partial Write • ROM Compiler: up to 512K bits per block • High-density single-port RAM 288K bits • Register file (2R/W, 2R/2W), up to 4,608 bits Phase-Locked Loops • Analog: up to 250 MHz (622 MHz under development) I/Os • 2.5V, 3.3V, and 5V tolerant • Slew-rate controlled • CMOS,TTL, PCML,T-LVTTL, LVDS, PCI, SSTL, GTL+,AGP, USB SOC IP Cores ARM 7TDMI Hard Macro ARC 32-bit RISC 834/836 SPARClite Hard Macros Oak DSP Hard Macro 10/100 MAC 64/256 QAM MPEG2 Decoder/Demultiplexer 8VSBTV Demodulator AC-3 DolbyVoice Decoder JPEG Encoder and Decoder PCI–33/66 MHz, 32/64-bit cores USB Host Controller/Device I2C IDE (ATA3) Host Controller Smart Card I/F IRDA I/R Interface More IPs are being added ASIC Design Kit and EDA Support Verilog Logic Simulators from Verilog-XL, NC-Verilog, Cadence, Synopsys, and Mentor VCS, Model-sim (Verilog) VHDL/VITAL Logic VSS, Model-sim (VHDL), V-System, Simulators from Synopsys, Leapfrog Cadence, and Mentor Synthesis, power, DFT, and Design Compiler, Design Power, Test STA tools from Synopsys Compiler, PrimeTime, MOTIVE, and Sunrise TestGen Other EDA tools Chrysalis Design Verifyer and Sente Watt Watcher CE71 Series Embedded Array Fujitsu Microelectronics, Inc. |
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