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MC1451A Datasheet(PDF) 25 Page - List of Unclassifed Manufacturers

Part # MC1451A
Description  Advanced Step Motor Control Chipset
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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MC1451A Datasheet(HTML) 25 Page - List of Unclassifed Manufacturers

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uses 1/216 scaling. Therefore we would send a value of 485 (decimal)
to the chipset.
All MC1451-series chips have the same cycle time (330 uSec),
which is not adjustable by the host.
Host Communications
Electrical Interface
The MC1451A communicates to the host processor via an 8-bit bi-
directional data port. 5* additional signals are used to synchronize
communication operations. The following table gives a brief description
of the control signals used during host communication:
Signal
Description
~HostSlct
Selects the host port for operations
~HostWrite
Writes a byte of data (or a command) to the chip
set. A write operation can only occur when the
ready/busy line indicates ready
~HostRead
Reads a byte of data from the chip set. A read
operation can only occur when the ready/busy line
indicates ready
HostCmd
Is asserted in combination with the HostWrite signal
when a command is being written to the chip set.
HostRdy
Indicates to the host that the host port is available
for operations
*An additional signal, HostIntrpt is provided to the host. This
signal is not used directly in communication operations, and is
discussed in a separate section
Three types of hardware communication operations are possible
between the host processor and the chip set; Command Write, Data
Write and Data Read. Each of these operations transfers information to
or from the chip set, and is coordinated using the 5 control signals listed
above.
A Command Write operation involves the transfer of a single byte
command to the chip set. To perform a write command operation, the
desired command is loaded on the 8 data pins and ~HostSlct and
~HostWrite are brought low, while HostCmd is brought high.
A Data Write operation involves the transfer of two bytes of data (1
word) to the chip set. To transfer the first byte (high byte), the desired
data byte is loaded on the 8 data bits and ~HostSlct, ~HostWrite and
HostCmd are brought low. The HostWrite signal is then brought high to
end the transfer of the first byte. To transfer the second byte (low byte),
the desired data byte is loaded on the 8 data bits and ~HostSlct,
~HostWrite and HostCmd are again brought low.
A Data Read operation involves the transfer of two bytes of data (1
word) from the chip set to the host. To transfer the first (high) byte,
~HostSlct, ~HostRead,and ~HostCmd signals should be brought low,
and the data should be read from the 8 bit data bus. The HostRead
signal is then brought high to end the transfer of the first byte. To
transfer the second (low) byte, ~HostSlct, ~HostRead, and ~HostCmd
are again brought low and the data should be read from the data bus.
Before any command write, data write or data read operations are
performed, the user must check that the HostRdy signal indicates
ready. After a command write, or after the second byte of each
read or write, this signal will go busy. It will return to ready when
the chipset can receive another I/O operation.
For more specific electrical information on the host interface operations,
see the pin descriptions and the timing diagram.
Packet Format
All communications to/from the chip set take the form of packets. A
packet is a sequence of transfers to/from the host resulting in a chip set
action or data transfer. Packets can consist of a command with no data
(Dataless Command), a command with associated data that is written
to the chip set (Write Command) or a command with associated data
that is read from the chip set (Read Command).
All commands with associated data (read or write) have either 1 or 2
words of data. See the host commands section for more information on
the length of specific commands.
If a read or a write command has 2 words of associated data (a 32 bit
quantity) the high word is loaded/read first, and the low word is
loaded/read second.
The following charts show the generic command packet sequence for a
Dataless Command, a Write Command, and a Read Command. The
hardware communication operation described in the previous section to
accomplish each type of transfer is shown in the left column.
Dataless Command
Time
-->
-->
-->
-->
Cmd Write:
Cmd byte
Data Write:
Data Read:
[pkt checksum]
Write Command
Time
-->
-->
-->
-->
Cmd Write:
Cmd byte
Data Write:
word 1 [word 2]
Data Read:
[pkt checksum]


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