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MT9LSDT872 Datasheet(PDF) 3 Page - Micron Technology

Part No. MT9LSDT872
Description  SYNCHRONOUS DRAM MODULE
Download  18 Pages
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Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

MT9LSDT872 Datasheet(HTML) 3 Page - Micron Technology

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8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
ZM28_3.p65 – Rev. 4/00
©1999,MicronTechnology,Inc.
8, 16 MEG x 72
REGISTERED SDRAM DIMMs
ADVANCE
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (Fig-
ures 1 and 2).
SPD START CONDITION
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has
been met.
SPD STOP CONDITION
All communications are terminated by a stop con-
dition, which is a LOW-to-HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the SPD device into standby power mode.
SPD ACKNOWLEDGE
Acknowledge is a software convention used to
indicate successful data transfers. The transmitting
device, either master or slave, will release the bus after
transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 3).
The SPD device will always respond with an ac-
knowledge after recognition of a start condition and
its slave address. If both the device and a WRITE
operation have been selected, the SPD device will re-
spond with an acknowledge after the receipt of each
subsequent eight-bit word. In the read mode the SPD
device will transmit eight bits of data, release the SDA
line and monitor the line for an acknowledge. If an
acknowledge is detected and no stop condition is
generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the
slave will terminate further data transmissions and
await the stop condition to return to standby power
mode.
SCL
SDA
DATA STABLE
DATA STABLE
DATA
CHANGE
Figure 1
Data Validity
SCL
SDA
START
BIT
STOP
BIT
Figure 2
Definition of Start and Stop
SCL from Master
Data Output
from Transmitter
Data Output
from Receiver
9
8
Acknowledge
Figure 3
Acknowledge Response from Receiver


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