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MT9LSDT872 Datasheet(PDF) 2 Page - Micron Technology

Part No. MT9LSDT872
Description  SYNCHRONOUS DRAM MODULE
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Maker  MICRON [Micron Technology]
Homepage  http://www.micron.com
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MT9LSDT872 Datasheet(HTML) 2 Page - Micron Technology

 
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8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
ZM28_3.p65 – Rev. 4/00
©1999,MicronTechnology,Inc.
8, 16 MEG x 72
REGISTERED SDRAM DIMMs
ADVANCE
GENERAL DESCRIPTION
The MT9LSDT872 and MT9LSDT1672 are high-speed
CMOS, dynamic random-access, 64MB and 128MB
memories organized in a x72 configuration. These mod-
ules use internally configured quad-bank SDRAMs with
a synchronous interface (all signals are registered on the
positive edge of clock signals CK0).
Read and write accesses to the SDRAM modules are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used to
select the bank and row to be accessed (BA0, BA1 select
the bank, A0-A11 select the row). The address bits
registered coincident with the READ or WRITE com-
mand are used to select the starting column location for
the burst access.
These modules provide for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst se-
quence.
These modules use an internal pipelined architecture
to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but
it also allows the column address to be changed on every
PART NUMBERS
PARTNUMBER
CONFIGURATION
SYSTEM BUS SPEED
MT9LSDT872G-13E__
8 Meg x 72
133MHz
MT9LSDT872G-133__
8 Meg x 72
133MHz
MT9LSDT872G-10E__
8 Meg x 72
100MHz
MT9LSDT1672G-13E__
16 Meg x 72
133MHz
MT9LSDT1672G-133__
16 Meg x 72
133 MHz
MT9LSDT1672G-10E__
16 Meg x 72
100 MHz
NOTE:
All part numbers end with a two-place code (not
shown), designating component and PCB revisions.
Consult factory for current revision codes. Example:
MT9LSDT1672G-133B1
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other
three banks will hide the PRECHARGE cycles and pro-
vide seamless, high-speed, random-access operation.
These modules are designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
SDRAM modules offer substantial advances in DRAM
operating performance, including the ability to
synchronously burst data at a high data rate with
automatic column-address generation, the ability to
interleave between internal banks in order to hide
precharge time, and the capability to randomly change
column addresses on each clock cycle during a burst
access. For more information regarding SDRAM opera-
tion, refer to the 64Mb and 128Mb SDRAM data sheets.
PLL AND REGISTER OPERATION
These modules can be operated in either registered
mode (REGE pin HIGH), where the control/address
input signals are latched in the register on one rising
clock edge and sent to the SDRAM devices on the
following rising clock edge (data access is delayed by one
clock), or in buffered mode (REGE pin LOW) where the
input signals pass through the register/buffer to the
SDRAM devices on the same clock. A phase-lock loop
(PLL) on the modules is used to redrive the clock signals
to the SDRAM devices to minimize system clock loading
(CK0 is connected to the PLL, and CK1, CK2 and CK3 are
terminated).
SERIAL PRESENCE-DETECT OPERATION
These modules incorporate serial presence-detect
(SPD). The SPD function is implemented using a 2,048-
bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes can be programmed by
Micron to identify the module type and various SDRAM
organizations and timing parameters. The remaining
128 bytes of storage are available for use by the customer.
System READ/WRITE operations between the master
(system logic) and the slave EEPROM device (DIMM)
occur via a standard IIC bus using the DIMM’s SCL
(clock) and SDA (data) signals, together with SA(2:0),
which provide eight unique DIMM/EEPROM addresses.


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