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MT9LSDT872 Datasheet(PDF) 13 Page - Micron Technology

Part No. MT9LSDT872
Description  SYNCHRONOUS DRAM MODULE
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Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

MT9LSDT872 Datasheet(HTML) 13 Page - Micron Technology

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8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
ZM28_3.p65 – Rev. 4/00
©1999,MicronTechnology,Inc.
8, 16 MEG x 72
REGISTERED SDRAM DIMMs
ADVANCE
SDRAM COMPONENT* AC ELECTRICAL CHARACTERISTICS
(Notes: 2, 3, 4, 5, 6, 7)
ACCHARACTERISTICS
-13E
-133
-10E
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTES
Access time from CLK
CL = 3
tAC
5.4
5.4
6
ns
8
(positive edge)
CL = 2
tAC
5.4
6
6
ns
Address hold time
tAH
0.8
0.8
1
ns
Address setup time
tAS
1.5
1.5
2
ns
CLK high level width
tCH
2.5
2.5
3
ns
CLK low level width
tCL
2.5
2.5
3
ns
Clock cycle time
CL = 3
tCK
7
7.5
8
ns
9
CL = 2
tCK
7.5
10
10
ns
9
CKE hold time
tCKH
0.8
0.8
1
ns
CKE setup time
tCKS
1.5
1.5
2
ns
CS#, RAS#, CAS#, WE#, DQM hold time
tCMH
0.8
0.8
1
ns
CS#, RAS#, CAS#, WE#, DQM setup time
tCMS
1.5
1.5
2
ns
Data-in hold time
tDH
0.8
0.8
1
ns
Data-in setup time
tDS
1.5
1.5
2
ns
Data-out high-impedance time
CL = 3
tHZ
5.4
5.4
6
ns
10
CL = 2
tHZ
5.4
6
7
ns
10
Data-out low-impedance time
tLZ
111
ns
Data-out hold time (load)
tOH
2.7
2.7
3
ns
Data-out hold time (no load)
tOH
N
1.8
1.8
1.8
ns
11
ACTIVE to PRECHARGE command
tRAS
37
120,000
44
120,000
50
120,000
ns
ACTIVE to ACTIVE command period
tRC
60
66
70
ns
ACTIVE to READ or WRITE delay
tRCD
152020
ns
Refresh period (4,096 cycles)
tREF
64
64
64
m s
AUTO REFRESH PERIOD
`tRFC
66
66
70
ns
PRECHARGE command period
tRP
15
20
20
ns
ACTIVE bank A to ACTIVE bank B command
tRRD
141520
ns
Transition time
tT
0.3
1.2
0.3
1.2
0.3
1.2
ns
12
WRITE recovery time
tWR
1 CLK +
1 CLK +
1 CLK +
13
7ns
7.5ns
7ns
14
15
15
ns
14
Exit SELF REFRESH to ACTIVE command
tXSR
67
75
80
ns
CAPACITANCE
PARAMETER
SYMBOL
MAX UNITS
Input Capacitance: A0-A11, BA0, BA1, RAS#, CAS#, WE#
CI1
8p F
Input Capacitance: S0#, S2#, CKE0, DQMB0#-DQMB7#
CI2
8p F
Input Capacitance: CK0
CI3
6p F
Input Capacitance: REGE
CI4
5p F
Input Capacitance: SCL, SA0-SA2, WP
CI5
12
p F
Input/Output Capacitance: DQ0-DQ63, CB0-CB7, SDA
CIO
8p F
*Specifications for the SDRAM components used on the module.
NOTE: This parameter is sampled. VDD = +3.3V; f = 1 MHz.


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