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MT9LSDT872 Datasheet(PDF) 5 Page - Micron Technology

Part No. MT9LSDT872
Description  SYNCHRONOUS DRAM MODULE
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Maker  MICRON [Micron Technology]
Homepage  http://www.micron.com
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MT9LSDT872 Datasheet(HTML) 5 Page - Micron Technology

 
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5
8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
ZM28_3.p65 – Rev. 4/00
©1999,MicronTechnology,Inc.
8, 16 MEG x 72
REGISTERED SDRAM DIMMs
ADVANCE
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
27, 111, 115
WE#, CAS#,
Input
Command Inputs: WE#, RAS#, and CAS# (along with S0#, S2#)
RAS#
define the command being entered.
42, 79, 125, 163
CK0-CK3
Input
Clock: CK0 is distributed through an on-board PLL to all devices.
CK1-CK3 are terminated.
128
CKE0
Input
Clock Enable: CKE0 activates (HIGH) and deactivates (LOW) the
CK0 signal. Deactivating the clock provides POWER-DOWN and
SELF REFRESH operation (all banks idle) or CLOCK SUSPEND
operation (burst access in progress). CKE0 is synchronous except
after the device enters power-down and self refresh modes,
where CKE0 becomes asynchronous until after exiting the same
mode. The input buffers, including CK0, are disabled during
power-down and self refresh modes, providing low standby
power.
30, 45
S0#, S2#
Input
Chip Select: S0#, S2# enable (registered LOW) and disable
(registered HIGH) the command decoder. All commands are
masked when S0#, S2# are registered HIGH. S0#, S2# are
considered part of the command code.
28-29, 46-47,
DQMB0-
Input
Input/Output Mask: DQMB is an input mask signal for write
112-113, 130-131
DQMB7
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-clock
latency) when DQMB is sampled HIGH during a READ cycle.
122, 39
BA0, BA1
Input
Bank Address: BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
33, 117, 34, 118, 35, 119,
A0-A11
Input
Address Inputs: A0-A11 are sampled during the ACTIVE command
36, 120, 37, 121, 38, 123
(row-address A0-A11) and READ/WRITE command (column-address
A0-A8/A9, with A10 defining auto precharge) to select one
location out of the memory array in the respective bank. A10 is
sampled during a PRECHARGE command to determine if both
banks are to be precharged (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE REGISTER command.
8 1
W P
Input
Write Protect: Serial presence-detect hardware write protect.
8 3
SCL
Input
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
165-167
SA0-SA2
Input
Presence-Detect Address Inputs: These pins are used to configure
the presence-detect device.
147
REGE
Input
Register Enable.
2-5, 7-11, 13-17, 19-20,
DQ0-DQ63
Input/
Data I/Os: Data bus.
55-58, 60, 65-67, 69-72,
Output
74-77, 86-89, 91-95,
97-101, 103-104,
139-142, 144, 149-151,
153-156, 158-161
21-22,0 52-53, 105-106,
CB0-CB7
Input/
Check Bits.
136-137
Output


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