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IS41C16128 Datasheet(PDF) 6 Page - Integrated Silicon Solution, Inc

Part No. IS41C16128
Description  128K x 16 (2-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
Download  21 Pages
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Maker  ISSI [Integrated Silicon Solution, Inc]
Homepage  http://www.issi.com
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IS41C16128 Datasheet(HTML) 6 Page - Integrated Silicon Solution, Inc

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IS41C16128
6
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
ISSI®
ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed
Min.
Max.
Unit
IIL
Input Leakage Current
Any input 0V < VIN < 5.5V
–10
10
µA
Other inputs not under test = 0V
IIO
Output Leakage Current
Output is disabled (Hi-Z)
–10
10
µA
0V < VOUT < 5.5V
VOH
Output High Voltage Level
IOH = –2.5 mA
2.4
V
VOL
Output Low Voltage Level
IOL = +2.1 mA
0.4
V
ICC1
Stand-by Current: TTL
RAS, LCAS, UCAS ≥ VIH
—2
mA
ICC2
Stand-by Current: CMOS
RAS, LCAS, UCAS ≥ VCC – 0.2V
1
mA
ICC3
Operating Current:
RAS, LCAS, UCAS,
-35
230
mA
Random Read/Write(2,3,4)
Address Cycling, tRC = tRC (min.)
-40
130
Average Power Supply Current
-45
120
-50
110
-60
100
ICC4
Operating Current:
RAS = VIL, LCAS, UCAS,
-35
220
mA
EDO Page Mode(2,3,4)
Cycling tPC = tPC (min.)
-40
90
Average Power Supply Current
-45
85
-50
80
-60
70
ICC5
Refresh Current:
RAS Cycling, LCAS, UCAS ≥ VIH
-35
230
mA
RAS-Only(2,3)
tRC = tRC (min.)
-40
130
Average Power Supply Current
-45
120
-50
100
-60
100
ICC6
Refresh Current:
RAS, LCAS, UCAS Cycling
-35
230
mA
CBR(2,3,5)
tRC = tRC (min.)
-40
130
Average Power Supply Current
-45
120
-50
100
-60
100
Notes:
1. An initial pause of 200
µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight
RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.


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