Electronic Components Datasheet Search
  English  ▼

Delete All


Preview PDF Download HTML

IS41C16128 Datasheet(PDF) 4 Page - Integrated Silicon Solution, Inc

Part No. IS41C16128
Description  128K x 16 (2-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
Download  21 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  ISSI [Integrated Silicon Solution, Inc]
Homepage  http://www.issi.com

IS41C16128 Datasheet(HTML) 4 Page - Integrated Silicon Solution, Inc

Zoom Inzoom in Zoom Outzoom out
 4 / 21 page
background image
Integrated Silicon Solution, Inc.
Functional Description
The IS41C16128 is a CMOS DRAM optimized for high-
speed bandwidth, low power applications. During READ
or WRITE cycles, each bit is uniquely addressed through
the 17 address bits. The row address is latched by the
Row Address Strobe (
RAS). The column address is
latched by the Column Address Strobe (
CAS). RAS is
used to latch the first nine bits and
CAS is used to latch the
latter nine bits.
The IS41C16128 has two
CAS controls, LCAS and UCAS.
LCAS and UCAS inputs internally generates a CAS
signal functioning in an identical manner to the single
input on the other 128K x 16 DRAMs. The key difference
is that each
CAS controls its corresponding I/O tristate
logic (in conjunction with
OE and WE and RAS). LCAS
controls I/O0 through I/O7 and
UCAS controls I/O8
through I/O15.
The IS41C16128
CAS function is determined by the first
CAS (LCAS or UCAS) transitioning LOW and the last
transitioning back HIGH. The two
CAS controls give the
IS41C16128 both BYTE READ and BYTE WRITE cycle
Memory Cycle
A memory cycle is initiated by bring
RAS LOW and it is
terminated by returning both
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS or OE,
whichever occurs last, while holding
column address must be held for a minimum time speci-
fied by tAR. Data Out becomes valid only when tRAC, tAA,
tCAC and tOEA are all satisfied. As a result, the access time
is dependent on the timing relationships between these
Write Cycle
A write cycle is initiated by the falling edge of
CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS or WE, whichever occurs
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory.
1. By clocking each of the 512 row addresses (A0 through
A8) with
RAS at least once every 8 ms. Any read, write,
read-modify-write or
RAS-only cycle refreshes the ad-
dressed row.
2. Using a
CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding
CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 256 columns within
a selected row to be randomly accessed at a high data
In EDO page mode read cycle, the data-out is held to the
CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the
CAS cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the
cycle time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one
RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
After application of the VCC supply, an initial pause of
µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that
RAS track with
VCC or be held at a valid VIH to avoid current surges.

Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21 

Datasheet Download

Link URL

Privacy Policy
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com

Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn