Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

PEB2025 Datasheet(PDF) 10 Page - Siemens Semiconductor Group

Part No. PEB2025
Description  ISDN Exchange Power Controller
Download  21 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  SIEMENS [Siemens Semiconductor Group]
Direct Link  http://www.siemens.com/
Logo SIEMENS - Siemens Semiconductor Group

PEB2025 Datasheet(HTML) 10 Page - Siemens Semiconductor Group

Back Button PEB2025 Datasheet HTML 6Page - Siemens Semiconductor Group PEB2025 Datasheet HTML 7Page - Siemens Semiconductor Group PEB2025 Datasheet HTML 8Page - Siemens Semiconductor Group PEB2025 Datasheet HTML 9Page - Siemens Semiconductor Group PEB2025 Datasheet HTML 10Page - Siemens Semiconductor Group PEB2025 Datasheet HTML 11Page - Siemens Semiconductor Group PEB2025 Datasheet HTML 12Page - Siemens Semiconductor Group PEB2025 Datasheet HTML 13Page - Siemens Semiconductor Group PEB2025 Datasheet HTML 14Page - Siemens Semiconductor Group Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 21 page
background image
Semiconductor Group
10
PEB 2025
Digital Part
The microprocessor interface (MPI) communicates with a processor which controles the IEPC. This
MPI contains a 3-bit data bus, a 2-bit address bus, read-, write-, chip select- and reset lines.
If chip select is inactive (logic high) the data bus is in a high impedance state and no communication
between the processor and IEPC is possible.
The IEPC contains a line oriented register architecture, i.e. one read and one write register for each
line. A read or write cycle affects the addressed register, which is related to the corresponding line
driver.
The write register consists of three control bits per line i:
D0: Automatic Restart-bit (AR)
D1: ON/OFF-bit (ON)
D2: must be 0
The read register consists of three status bits per line i:
D0: Interrupt-bit (INT)
D1: Actual ON/OFF Driver status-bit (AO)
D3: Current Overload-bit (CO)
A logic high on the RES pin sets the device into an inital state: all registers of the IEPC are cleared
(D0i - D2i are low).
Figure 5
Open Loop Detection


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn