TPS40140 datasheet(12/65 Pages) TI | DUAL OR 2-PHASE, STACKABLE CONTROLLER

Part #	TPS40140

Description	DUAL OR 2-PHASE, STACKABLE CONTROLLER

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Manufacturer	TI [Texas Instruments]

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4.3 VOLTAGE MASTER AND VOLTAGE SLAVE

4.3.1

TERMINAL FUNCTIONS

TPS40140

DUAL OR 2-PHASE, STACKABLE CONTROLLER

SLUS660A – SEPTEMBER 2005 – REVISED JULY 2006

A Voltage Master has the channel that monitors the output voltage and generates the 'COMP' signal for

voltage regulation. A Voltage Slave channel is configured by connecting the TRKx pin to BP5. Then the

COMP signal from the Master is connected to the COMPx pin on the Voltage Slave. When the TRKx pin is

connected to BP5 the COMPx output for that channel is put in a high impedance state, allowing the

regulation for that channel to be controlled by the Voltage Master COMP signal.

Table 4-1. TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Filtered input from the VREG pin. A 10-

Ω resistor should be connected between VREG and BP5 and a

BP5

8

O

1.0-

µF ceramic capacitor should be connected from BP5 to ground.

GND

7

-

Low noise ground connection to the device.

BOOT1 provides a bootstrapped supply for the high side FET driver for PWM1, enabling the gate of the

BOOT1

27

I

high side FET to be driven above the input supply rail. Connect a capacitor from BOOT1 to SW1 pin and

a Schottky diode from this pin to VREG.

BOOT2 provides a bootstrapped supply for the high side FET driver for PWM2, enabling the gate of the

BOOT2

18

I

high side FET to be driven above the input supply rail. Connect a capacitor from BOOT2 to SW2 pin and

a Schottky diode from this pin to VREG.

Digital clock signal for synchronizing slave controllers to the master CLKIO frequency and is either 6 or 8

CLKIO

28

O

times the PWM switching frequency.

COMP1

35

O

Output of the error amplifier, CH1. The voltage at this pin determines the duty cycle for the PWM1.

COMP2

10

O

Output of the error amplifier, CH2. The voltage at this pin determines the duty cycle for the PWM2.

These pins are used to sense the CH1 phase current. Inductor current can be sensed with an external

CS1

31

I

current sense resistor or by using an external R-C circuit and the inductor’s DC resistance. The traces for

these signals must be connected directly at the current sense element.

These pins are used to sense the CH2 phase current. Inductor current can be sensed with an external

CS2

14

I

current sense resistor or by using an external R-C circuit and the inductor’s DC resistance. The traces for

these signals must be connected directly at the current sense element.

Return point of CH1 current sense voltage. The trace for this signal must be connected directly at the

CSRT1

32

O

current sense element.

Return point of CH1 current sense voltage. The trace for this signal must be connected directly at the

CSRT2

13

O

current sense element.

Output of the differential amplifier. The output voltage of the differential amplifier is limited to 5.8 V. For

remote sensing, the voltage at this pin represents the true output voltage without I

× R drops that result

DIFFO

1

O

from high current in the PCB traces. The VOUT and GSNS pins must be connected directly at the point of

load where regulation is required. See Layout Guidelines for more information.

Inverting input of the error amplifier for CH1. In closed loop operation, the voltage at this pin is nominally

FB1

36

I

700 mV. This pin is also monitored for PGOOD1 and undervoltage on CH1.

Inverting input of the error amplifier for CH2. In closed loop operation, the voltage at this pin is nominally

FB2

9

I

700 mV. This pin is also monitored for PGOOD2 and undervoltage on CH2.

Inverting input of the differential amplifier. This pin should be connected to ground at the load. If the

GSNS

3

I

differential amplifier is not used, tie this pin to GND or leave open.

Gate drive output for the high side N-channel MOSFET switch for CH1. Output is referenced to SW1 and

HDRV1

26

O

is bootstrapped for enhancement of the high side switch.

Gate drive output for the high side N-channel MOSFET switch for CH2. Output is referenced to SW2 and

HRDV2

19

O

is bootstrapped for enhancement of the high side switch.

Used to set the cycle-by-cycle current limit threshold for CH1. If the ILIM1 threshold is reached, the PWM

ILIM1

34

I

pulse is terminated and the converter delivers limited current to the output.

Used to set the cycle-by-cycle current limit threshold for CH2. If the ILIM2 threshold is reached, the PWM

ILIM2

11

I

pulse is terminated and the converter delivers limited current to the output.

LRDV1

24

O

Gate drive output for the low side synchronous rectifier (SR) N-channel MOSFET for CH1.

LRDV2

22

O

Gate drive output for the low side synchronous rectifier (SR) N-channel MOSFET for CH2.

DEVICE INFORMATION

12

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