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TPS40140 Datasheet(PDF) 49 Page - Texas Instruments

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Part No. TPS40140
Description  DUAL OR 2-PHASE, STACKABLE CONTROLLER
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPS40140 Datasheet(HTML) 49 Page - Texas Instruments

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6.2 Example 2: Two-Phase Single Output Configuration From 12 V to 1.5 V DC/DC Converter
6.2.1
Step 1: Output Capacitor Selection
Õ
Õ
PH
PH
N
PH
i=1
OUT
PH
N
-1
PH
i=1
i - N
× D
I
(N
, D) =
( i - N
× D + 1)
(36)
I
RIPPLE +
V
OUT
L
f
SW
DIOUT NPH, D + 4.374 A
(37)
6.2.2
Step 2: Input Capacitor Selection
TPS40140
DUAL OR 2-PHASE, STACKABLE CONTROLLER
SLUS660A – SEPTEMBER 2005 – REVISED JULY 2006
Using a TPS40140
The following example illustrates the design process and component selection for a two phase single
output synchronous buck converter using TPS40140. The design goal parameters are given in Table 6-2.
The inductor and MOSFET selection equations are quite similar to the dual output converter design, so
they will not be repeated here.
Table 6-2. Design Goal Parameters
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VIN
Input Voltage
10.8
12
13.2
V
VOUT
Output voltage
1.5
V
VRIPPLE
Output ripple
IO = 32A
2%Vo
V
IOUT1
Output current
32
A
fsw
Switching frequency
500
kHz
The output capacitor is typically selected by the output load transient response requirement. Equation 3 in
the dual output design example is used. The inductor L in the equation will be equal to the phase
inductance divided by number of phases.
Based on a 15-A load transient with a maximum of 30 mV deviation, a minimum 1.32-
µF output capacitor
is required. In the design, four 330-
µF, 2 V, SP capacitor are selected to meet this requirement. Each
capacitor has an ESR of 6 m
Ω.
Another criterion for capacitor selection is the output ripple voltage that is determined mainly by the
capacitance and the ESR.
Due to the interleaving of channels, the total output ripple current is smaller than the ripple current from a
single phase. The ripple cancellation factor is expressed in Equation 36.
Where:
D is the duty cycle for a single phase
N
PH is the number of active phases, here it is equal to 2
Then the maximum output ripple current is calculated by:
With 1.32 mF output capacitance, the ripple voltage at the capacitor is calculated to be 828
µV. In the
specification, the output ripple voltage should be less than 30mV, so based on Equation 4, the required
maximum ESR is 6.7 m
Ω. The selected capacitors can meet this requirement.
The input voltage ripple depends on the input capacitance and the ESR. The minimum capacitor and the
maximum ESR can be estimated by Equation 5 and Equation 6 in the dual output design example.
For this design, VRIPPLE(CIN) assume is 100mV and VRIPPLE(CinESR) is 50mV, also the inductor ripple current
IRIPPLEwill is 30%, so the calculated minimum capacitance is 40µF and the maximum ESR is 2.7 mΩ.
Choosing four 22-
µF, 16-V, 2-mΩ ESR ceramic capacitors meet this requirement.
Submit Documentation Feedback
DESIGN EXAMPLES
49


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