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TPS40140 Datasheet(PDF) 40 Page - Texas Instruments

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Part No. TPS40140
Description  DUAL OR 2-PHASE, STACKABLE CONTROLLER
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPS40140 Datasheet(HTML) 40 Page - Texas Instruments

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5.28.1 BASIC CONFIGURATIONS FOR 2, 4, 6, 8, 12 OR 16 PHASES
5.28.2 CONFIGURING FOR OTHER NUMBER OF PHASES
M_CH1
M_CH2
S_CH1
S_CH2−
NOT USED IN3PH
M
R
S
TPS40140
DUAL OR 2-PHASE, STACKABLE CONTROLLER
SLUS660A – SEPTEMBER 2005 – REVISED JULY 2006
The solid square boxes in Figure 5-20 represent the PHSEL pin of the Master (M) controller or a
numbered Slave controller (S1-S7). The labels on the spokes of the wheels indicate a Master Channel 1
and Master Channel 2 (M_CH1 and M_CH2) and numbered Slaves Channel 1 and Slave Channel 2
(Sn_CH1 and Sn_CH2). The Channel 1 and Channel 2 of a given Master or Slave is always 180
° out of
phase.
The Master and Slaves are automatically configured for proper phasing based on the resistor string from
the Master to the Slaves. All the resistors are 39 k
Ω to 41.2 kΩ. Part (A) above shows a single controller
operating two phases 180
° out of phase. Part (B) above shows four phase operation. This is configured by
connecting a single resistor from the Master PHSEL to GND and grounding the Slave PHSEL pin. The
individual channels are 90
° out of phase. Part (C) above shows six phase operation. This is configured by
connecting two resistors from the Master PHSEL to GND. The first resistor tap is connected to Slave2
PHSEL pin and then grounding the Slave1 PHSEL pin. The individual channels are 60
°out of phase. Part
(D) above shows eight phase operation. This is configured by connecting three resistors from the Master
PHSEL to GND. The first resistor tap is connected to Slave3 PHSEL pin. The second resistor tap is
connected to Slave2 PHSEL pin and then grounding the Slave1 PHSEL pin. The individual channels are
45
° out of phase. Part (F) above shows twelve phase operation. This is configured by connecting two
resistors from the Master PHSEL to GND. The Master PHSEL pin is also connected to Slave5 PHSEL pin.
The first resistor tap is connected to Slave2 and Slave4 PHSEL pins and then grounding the Slave1 and
Slave3 PHSEL pins. The individual channels are 30
° out of phase. Additionally, the ILIM2 pins of Slave5,
Slave4 and Slave3 are left open (internal pull-up) or externally connected to BP5. Part (G) above shows
sixteen phase operation. This is configured by connecting three resistors from the Master PHSEL to GND.
The Master PHSEL pin is also connected to Slave7 PHSEL pin. The first resistor tap is connected to
Slave3 and Slave6 PHSEL pins. The second resistor tap is connected to Slave2 and Slave5 PHSEL pins
and then grounding the Slave1 and Slave4 PHSEL pins. The individual channels are 22.5
° out of phase.
Additionally, the ILIM2 pins of Slave7, Slave6, Slave5 and Slave4 are left open (internal pull-up) or
externally connected to BP5.
Configuring for other than 2, 4, 6, 8, 12 or 16 phases is simply a matter of not attaching one or more Slave
controllers. The phasing between Master and populated Slaves is as shown above. For example a
3-phase system could be configured with a Master CH1 and Master CH2 and 1 phase of a Slave.
Referring to part (B) above, the 3 phases could be Master CH1, Master CH2 and Slave CH1 or Slave CH2
as shown in Figure 5-21.
Figure 5-21. Phase System: 2 Channels of the Master and 1 Channel of the Slave
The 3-phase system could also be configured with 1 channel of the Master and 2 channels of the Slave.
Referring to part (B) above, the 3 phases could be Master CH1 or Master CH2 and Slave CH1 and Slave
CH2. In either of these configurations there will be 90
° between two of the channels and 180° between the
other channel. The unused channel could be another independent output voltage whose clocking would
occupy the phase not used in the 3-phase system. This philosophy can be used for any number of phases
not shown in Figure 5-20, Clock Phasing Summary.
For example, a 10-phase system could be configured as shown in Figure 5-22.
APPLICATION INFORMATION
40
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