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SN74SSTE32882 Datasheet(PDF) 5 Page - Texas Instruments

Part No. SN74SSTE32882
Description  28-Bit to 56-Bit Registered Buffer With Address Parity Test and One Pair to Four Pair Differential Clock PLL Driver
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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SN74SSTE32882 Datasheet(HTML) 5 Page - Texas Instruments

   
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
(1)
SN74SSTE32882
SCAS840 – NOVEMBER 2006
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
UNIT
AVDD,
PVDD, or
Supply voltage range
–0.7 to 2.2
V
VDD
VI
Input voltage range(2)(3)
–0.5 to 2.2
V
VO
Output voltage range (1) (2)
–0.5 to VCC + 0.5
V
IIK
Input clamp current, (VI < 0 or VI > VCC)
±50
mA
IOK
Output clamp current, (VO < 0 or VO > VCC)
±50
mA
IO
Continuous output current (VO = 0 to VCC)
±50
mA
Continuous current through each VCC or GND
mA
θ
JA
Package thermal impedance(4)
TBD
TBD
Tstg
Storage temperature range
–65 to 150
°C
(1)
Stress beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3)
This value is limited to 2.2 V maximum.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7.
MIN
NOM
MAX
UNIT
VDD
DC supply voltage
1.425
1.5
1.575
V
PVDD
DC analog (PLL) output supply voltage
1.425
1.5
1.575
V
AVDD
DC PLL supply voltage (2)
PVDDQ
V
VREF
DC reference voltage (3)
0.49
× V
DD
0.5
× V
DD
0.51
× V
DD
V
VTT
DC termination voltage
VREF– 40 mV
VREF
VREF + 40 mV
V
VIH(AC)
AC high-level input voltage
VREF + 0.175
VDD + 0.3
V
VIL(AC)
AC low-level input voltage
–0.3
VREF– 0.175
V
Data (Dn), DCSn, DODTn, DCKEn, and
PAR_IN inputs
VIH(DC)
DC high-level input voltage
VREF +0.1
VDD
V
VIL(DC)
DC low-level input voltage
0
VREF– 0.1
V
VIH_CMOS
DC high-level input voltage
RESET
0.65
× V
DD
VDD
V
VIL_CMOS
DC low-level input voltage
RESET
0
0.35
× V
DD
V
1/2PVDD
VIX
Common-mode input voltage range
CLK, CLK, FBIN, FBIN
1/2PVDD– 0.175
1/2PVDD
V
+0.175
VID
Peak-to-peak input voltage
CLK, CLK, FBIN, FBIN
0.35
VDD + 0.6(4)
V
Qn, QCSn, WCKEn, QODTn
–TBD
IOH
High-level output current (5)
mA
QCLKn, QCLKn
–TBD
Qn, QCSn, WCKEn, QODTn
TBD
IOL
Low-level output current(5)
QCLKn, QCLKn
TBD
mA
QERR output
25
TA
Operating free-air temperature
0
90
°C
(1)
The RESET and DCn inputs of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The
differential inputs must not be floating unless RESET is low. See the TI application report, Implication of Slow or Floating CMOS Inputs
(SCBA004).
(2)
The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, PVDD remains within the
recommended operating condition and no timing parameters are ensured.
(3)
Stable Vref needs to be applied whenever RESET is high
(4)
The input voltage of each CLK, CLK, FBIN or FBIN pin must not exceed VIL(AC) minimum and VIH(AC) maximum.
(5)
Measured with CMR default settings.
5
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