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SN74SSTE32882 Datasheet(PDF) 4 Page - Texas Instruments |
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SN74SSTE32882 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 7 page ![]() www.ti.com REGISTER LOGIC DIAGRAM (POSITIVE LOGIC) 0 R Q Q 1 R Q Q ControlWord StateMachineand ControlLogic Address Inversion 3 4 DA0..DA2,DBA2 DA3..DA4,DBA0,DBA1 B-Enable A-Enable Y0.. Y3Enable 4 0 R Q Q 1 CE CE 180ps delay CMR Address Pre- Launch 0 R Q Q 1 180ps delay 0 R Q Q 1 180ps delay 0 R Q Q 1 180ps delay PLL Vref DA0..DA9, DA11, DA13..DA15, DBA0..DBA2 DA10..DA12, , , DRASDCAS DWE DCS0 DCS DCKE0, DCKE1 DODT0, DODT1 RESET CK CK 10kW 100kW FBIN FBIN QxA0..QxA9, QxA11, Qxa13..QxA15, QxBA0..QxBA2 QxA10, QxA12, , , QxRAS QxCAS QxWE QxCS0 QxCS1 QxCKE0, QxCKE1, QxODT0, QxODT1 Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 FBOUT FBOUT SN74SSTE32882 SCAS840 – NOVEMBER 2006 4 Submit Documentation Feedback |