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SN74SSTE32882 Datasheet(PDF) 3 Page - Texas Instruments

Part No. SN74SSTE32882
Description  28-Bit to 56-Bit Registered Buffer With Address Parity Test and One Pair to Four Pair Differential Clock PLL Driver
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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SN74SSTE32882 Datasheet(HTML) 3 Page - Texas Instruments

   
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SN74SSTE32882
SCAS840 – NOVEMBER 2006
TERMINAL FUNCTIONS (continued)
TERMINAL NAME
DESCRIPTION
ELECTRICAL TYPE
Chip-select gated D-inputs. Data inputs – Clocked in on the crossing of the rising
D0–D21
edge of CK and the falling edge of CK. Re-driven only when either DCS0 or DCS1
SSTL_15 inputs
is low.
Chip select inputs – These pins initiate DRAM address/command decodes, and as
such at least one will be low when a valid address/command is present. The
DCS0, DCS1
register can be programmed to redrive all D-inputs only when at least one chip
SSTL_15 inputs
select input is low. If DCS0 and DCS1 inputs are high, D-inputs will be ignored with
the Q outputs being floating or help at previous state.
Ungated inputs – The corresponding outputs of these register bit inputs will not be
DOTD0, DODT1
SSTL_15 inputs
suspended by the DCS0 and DCS1 control unless a CMR access occurs.
Ungated inputs – The corresponding outputs of these register bit inputs will not be
DCKE0, DCKE1
SSTL_15 inputs
suspended by the DCS0 and DCS1 control unless a CMR access occurs.
PAR_IN
Parity input – Arrives one clock cycle after the corresponding data input.
SSTL_15 inputs
YB0, YA0, YB1, YA1
Positive clock outputs
1.5 V CMOS output
YB0, YA0, YB1, YA1
Complementary clock outputs
1.5 V CMOS output
Positive feedback clock output
1.5 V CMOS output
FBOUT
Complementary feedback clock output
1.5 V CMOS output
Q0A–Q21A,
Data outputs corresponding to inputs D0 .. D21
1.5 V CMOS output
Q0B–Q21B
QCS0A, QCS0B,
Data outputs corresponding to inputs DCS0 and DCS1
1.5 V CMOS output
QCS1A, QCS1B
QOTD0A, QODT0B,
Data outputs corresponding to inputs DODT0 and DODT1
1.5 V CMOS output
QOTD1A, QODT1B
QCKE0A, QCKE0B,
Data outputs corresponding to inputs DCKE0 and DCKE1
1.5 V CMOS output
QCKE1A, QCKE1B
Output error – Generated three clock cycles after the corresponding data is
QERR
Open-drain output
registered.
3
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