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LMX2531LQ1500E Datasheet(PDF) 11 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. LMX2531LQ1500E
Description  High Performance Frequency Synthesizer System with Integrated VCO
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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LMX2531LQ1500E Datasheet(HTML) 11 Page - National Semiconductor (TI)

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2.0 General Programming Information
The LMX2531LQ1500E is programmed using 11 24-bit registers used to control the LMX2531LQ1500E operation. A 24-bit shift
register is used as a temporary register to indirectly program the on-chip registers. The shift register consists of a data field and
an address field. The last 4 register bits, CTRL[3:0] form the address field, which is used to decode the internal register address.
The remaining 20 bits form the data field DATA[19:0]. While LE is low, serial data is clocked into the shift register upon the rising
edge of clock (data is programmed MSB first). When LE goes high, data is transferred from the data field into the selected register
bank.
Although there are actually 14 registers in this part, only a portion of them should be programmed, since the state of the other
hidden registers (R13, R11, and R10) are set during the initialization sequence. Although it is possible to program these hidden
registers, as well as a lot of bits that are defined to either ’1’ or ’0’, the user should not experiment with these hidden registers and
bits, since doing will most likely degrade performance. Furthermore, this would be inconsistent to how these parts are tested.
DATA[19:0]
CONTROL[3:0]
MSB
LSB
D19
D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C3 C2 C1
C0
2.01 Register Location Truth Table
C3
C2
C1
C0
Data Address
1100
R12
1001
R9
1000
R8
0111
R7
0110
R6
0101
R5
0100
R4
0011
R3
0010
R2
0001
R1
0000
R0
2.02 Initialization Sequence
The initial loading sequence from a cold start is described below. The registers must be program in order shown.
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
987654321
0
DATA[19:0]
C3 C2 C1 C0
R5
INIT1
10000100000000000000010
1
R5
INIT2
10000000000000000000010
1
R5
10000000000001111111010
1
R12
00000001000001001000110
0
R9
See individual section for R9 programming information.
1
0
0
1
R8
See individual section for Register R8 programming information.
Register R8 only needs to be programmed for a few options of the LMX2531LQ1500E and
and only in the case that the OSCin frequency is greater than 40 MHz.
100
0
R7
See individual section for Register R7 programming information.
0
1
1
1
R6
See individual section for Register R6 programming information.
0
1
1
0
R4
See individual section for Register R4 programming information.
Register R4 only needs to be programmed if FastLock is used.
010
0
R3
See individual section for Register R3 programming information.
0
0
1
1
R2
See individual section for Register R2 programming information.
0
0
1
0
R1
See individual section for Register R1 programming information.
0
0
0
1
R0
See individual section for Register R0 programming information.
0
0
0
0
Note: There must be a minimum of 10 mS between the time when R5 is last loaded and when R1 is loaded to ensure time for
the LDOs to power up properly.
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