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TPS65040 Datasheet(PDF) 68 Page - Texas Instruments |
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TPS65040 Datasheet(HTML) 68 Page - Texas Instruments |
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68 / 72 page  CSPI CSPI Write Operation 1.5CCLK CCLK CDATA CSTB D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0 DataLatch TPS65040 SLVS708 – NOVEMBER 2006 default value when the CRESET pin becomes Low. It gives priority to TSP for the addresses of Table 24, although CSPI and TSP are also possible for writing two interfaces simultaneously. It is not possible to write from CSPI while TSP is writing to it. This operation is detected by the TSPEN signal. When TSPEN=Low, Table 24 priority operation goes active. The other addresses can be accessed from CSPI during TSPEN=Low. However, please note that writing from CSPI becomes effective when there is writing from CSPI to the same address, after writing TSP ends. Internal logic is able to operate between 2.7V and 3.1V. But the DC/DC converter, PAVREF and V11_V28TX should be OFF. Also V12_V28RX, V13_V28A, V15_V18A, VGGE1_V28, VGGE2_V28 and VGGE3_V28 should be OFF, or Low-power Mode. Table 24. TSP Priority Address of Write Operation CSPI TSP ADDRESS REG. NAME ADDRESS REG. NAME F0h AFCMSBW 0h AFCDATA F1h AFCLSBW ECh LDO Control for GGE 1h LDO Control for GGE F2h AFCDACCTL 2h AFCDACCTL CSPI is an interface that consists of three lines (CDATA pin, CCLK pin, and CSTB pin). It changes into the output mode only when reading data, although CDATA is usually an input mode. Data length becomes 16-BIT (8-BIT data, 8-BIT address). The WRITE format is shown in Figure 86 and the READ format is shown in Figure 87. The timing of READ/WRITE for CSPI operation is shown in Figure 88. The 8-BIT advance data becomes the WRITE operation, and the following 8-BIT group becomes an address by data. WRITE data is taken by the rising edge of CCLK, and reflected by the falling edge of CSTB. Figure 86. CSPI Write Format Notification is given when the data of AFCDAC is re-written by using CSPI. AFCDAC has a 12-bit data length. Since the data length of CSPI is 8-bit, it can not re-write the 12-bIt data by the one-time-access. Therefore, the data of AFCDAC is written by two-times-access from CSPI. F0h: r[AFCMSBW] is written first, and the next is F1h: r[AFCLSBW]. This process is described as: 1. Write data in F0h : r [AFCMSBW]. Write '0' in the first 4 bits. This data is insignificant. 2. Write data in F1h : r [AFCLSBW]. Note 1. If step 2 is done before step 1, the correct data will not be reflected. Note 2. If step 2 is done, but step 1 and step 2 are done sequentially, the correct data will be properly reflected. 68 Submit Documentation Feedback |
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