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TPS65040 Datasheet(PDF) 52 Page - Texas Instruments

Part # TPS65040
Description  CLOCK- AND POWER-MANAGEMENT IC FOR RF SYSTEM
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPS65040 Datasheet(HTML) 52 Page - Texas Instruments

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V_LNA_FEM
V13_V28A
TPS65040
SLVS708 – NOVEMBER 2006
mode is changed automatically. On/off for this LDO is controlled by register command r[PSCNT12], and
switching from normal mode to low-power mode is controlled with the WRFON pin. Register command
r[PSCNT12] can be controlled through the serial interface; the default is 1. Note: Turn off this LDO, or use
low-power mode when VBAT < 3.1 V. The SERIAL INTERFACE Section explains in more detail. The switch
control of normal mode/low-power mode, and V12_V28RX ON/OFF control is shown in Table 5.
Table 5. V12_V28RX ON/OFF and Normal Mode/Low Power Mode Control
REG_EN(1)
VIO1V8(1)
CRESET(1)
WRFON
r[PSCNT12]
V12_V28RX
1
1
1
1
1
Normal Mode
1
1
1
0
1
Low Power Mode
1
1
1
1
0
OFF
1
1
1
0
0
OFF
0
0
Don't Care
Don't Care
Don't Care
OFF
1
0
Don't Care
Don't Care
Don't Care
OFF
1
1
0
Don't Care
1
Normal Mode
(1)
REG_EN and VIO1V8 sequence is described in SEQUENCE CONTROL.
V_LNA_FEM is output from V12_V28RX through the R3V switch. Switch R3V controls on/off by the WRFON
pin, TXONFST pin, and r[PSCNTR3V]. Register command r[PSCNTR3V] can be controlled through the serial
interface; default is 0. The SERIAL INTERFACE Section provides more detail. On/off control of V_LNA_FEM is
shown in Table 6.
Table 6. V_LNA_FEM ON/OFF Control
REG_EN(1)
VIO1V8(1)
WRFON
r[PSCNT12]
r[PSCNTR3V]
V_LNA_FEM
1
1
1
1
1
ON
1
1
1
0
1
OFF
1
1
1
1
0
OFF
1
1
1
0
0
OFF
1
1
0
1
1
OFF
1
1
0
0
1
OFF
1
1
0
1
0
OFF
1
1
0
0
0
OFF
0
0
Don't Care
Don't Care
Don't Care
OFF
1
0
Don't Care
Don't Care
Don't Care
OFF
(1)
REG_EN, VIO1V8 and CRESET sequence is described in SEQUENCE CONTROL.
V13_V28A outputs 2.85V. This LDO is enabled during the power-up sequence of the TPS65040. The
SEQUENCE CONTROL Section provides more detail. Normal mode and low-power mode can be selected.
Normal mode provides high performance, and low-power mode provides low current consumption. The output
PMOS is stopped when the load current exceeds the limit value of the current-limit protection circuit in normal
mode, shutting down the power supply. When the load current falls to less than the limit values, current limit is
released. Current-limit protection is not available in low-power mode. This LDO has a low-current mode and a
high-current mode in normal mode. Under light-load conditions the mode is low-current. When under heavy-load
conditions, the mode is high current. Mode is changed automatically. This LDO on/off is controlled by
r[PSCNT13], and switches from normal mode to low-power mode with the WRFON pin. Register command
r[PSCNT13] can be controlled through the serial interface; default is 1. Note: Turn off this LDO, or use
low-power mode when VBAT < 3.1V. The SERIAL INTERFACE Section explains in greater detail. The switch
control of normal mode / low-power mode, and V13_V28A on/off control is shown in Table 7.
52
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