Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

TPS3808G125 Datasheet(PDF) 4 Page - Texas Instruments

Part No. TPS3808G125
Description  Low Quiescent Current, Programmable-Delay Supervisory Circuit
Download  15 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo 

TPS3808G125 Datasheet(HTML) 4 Page - Texas Instruments

 
Zoom Inzoom in Zoom Outzoom out
 4 / 15 page
background image
www.ti.com
Adjustable Voltage Version
Fixed Voltage Version
Reset
Logic
Timer
+
90k
V
DD
V
DD
GND
0.4V
V
REF
SENSE
MR
C
T
RESET
TPS3808G01
Adjustable Voltage
Reset
Logic
Timer
+
90k
V
DD
V
DD
GND
0.4V
V
REF
SENSE
MR
C
T
RESET
R
1
R
2
R
1 + R2 = 4MΩ
PIN ASSIGNMENTS
DBV PACKAGE
SOT23
(TOP VIEW)
VDD
SENSE
CT
RESET
GND
MR
1
2
3
6
5
4
RESET
GND
MR
6
5
4
V
DD
SENSE
C
T
1
2
3
DRV PACKAGE
2mm x 2mm QFN
(TOP VIEW)
Power
PAD
TPS3808
SBVS050F – MAY 2004 – REVISED OCTOBER 2006
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. Adjustable and Fixed Voltage Versions
Table 1. TERMINAL FUNCTIONS
TERMINAL
SOT23 (DBV)
NAME
PIN NO.
DESCRIPTION
RESET
1
RESET is an open drain output that is driven to a low impedance state when RESET is asserted (either the
SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low). RESET will
remain low (asserted) for the reset period after both SENSE is above VIT and MR is set to a logic high. A
pull-up resistor from 10k
Ω to 1MΩ should be used on this pin, and allows the reset pin to attain voltages
higher than VDD.
GND
2
Ground
MR
3
Driving the manual reset pin (MR) low asserts RESET. MR is internally tied to VDD by a 90kΩ pull-up
resistor.
CT
4
Reset period programming pin. Connecting this pin to VDD through a 40kΩ to 200kΩ resistor or leaving it
open results in fixed delay times (see Electrical Characteristics). Connecting this pin to a ground referenced
capacitor
≥ 100pF gives a user-programmable delay time. See Selecting The Reset Delay Time in the
Device Operation section for more information.
SENSE
5
This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold
voltage VIT, then RESET is asserted.
VDD
6
Supply voltage. It is good analog design practice to place a 0.1
µF ceramic capacitor close to this pin.
PowerPAD
PowerPAD. Connect to ground plane to enhance thermal performance of package.
4
Submit Documentation Feedback


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn