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MC1650 Datasheet(PDF) 1 Page - Motorola, Inc

Part No. MC1650
Description  DUAL A/D CONVERTER
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC1650 Datasheet(HTML) 1 Page - Motorola, Inc

 
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4–334
REV 5
© Motorola, Inc. 1996
3/93
Dual A/D Converter
The MC1650 and the MC1651 are very high speed comparators utilizing
differential amplifier inputs to sense analog signals above or below a reference
level. An output latch provides a unique sample-hold feature. The MC1650
provides high impedance Darlington inputs, while the MC1651 is a lower
impedance option, with higher input slew rate and higher speed capability.
The clock inputs (Ca and Cb) operate from MECL III or MECL 10,000 digital
levels. When Ca is at a logic high level, Q0 will be at a logic high level provided
that V1 u V2 (V1 is more positive than V2). Q0 is the logic complement of Q0.
When the clock input goes to a low logic level, the outputs are latched in their
present state.
Assessment of the performance differences between the MC1650 and the
MC1651 may be based upon the relative behaviors shown in Figures 4 and 7.
• PD = 330 mW typ/pkg (No Load)
• tpd = 3.5 ns typ (MC1650)
= 3.0 ns typ (MC1651)
• Input Slew Rate = 350 V/µs (MC1650)
= 500 V/
µs (MC1651)
• Differential Input Voltage: 5.0 V (–30°C to +85°C)
• Common Mode Range:
–3.0 V to +2.5 V (–30
°C to +85°C) (MC1651)
–2.5 V to +3.0 V (–30
°C to +85°C) (MC1650)
• Resolution: p 20 mV (–30°C to +85°C)
• Drives 50 Ω lines
Number at end of terminal denotes pin number for L package (Case 620).
LOGIC DIAGRAM
+
+
V1A 6
V2A 5
CA 4
V1B12
V2B 11
CB 13
2 Q0
3 Q0
14 Q1
15 Q1
VCC = +5.0 V = PIN 7, 10
VEE = –5.2 V = PIN 8
GND = PIN 1, 16
DQ
Q
D
Q
Q
TRUTH TABLE
C
V1 , V2
Q0n + 1
Q0n + 1
HV1 u V2
HL
HV1 t V2
LH
L
X
X
Q0n
Q0n
MC1650
MC1651
PIN ASSIGNMENT
GND
Q0
Q0
CA
V2A
V1A
VCC
VEE
GND
Q1
Q1
CB
V1B
V2B
VCC
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
L SUFFIX
CERAMIC PACKAGE
CASE 620–10


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