Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

M306V5ME-XXXSP Datasheet(PDF) 67 Page - Mitsubishi Electric Semiconductor

Part No. M306V5ME-XXXSP
Description  SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Download  262 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
Logo 

M306V5ME-XXXSP Datasheet(HTML) 67 Page - Mitsubishi Electric Semiconductor

Zoom Inzoom in Zoom Outzoom out
 67 / 262 page
background image
M306V5ME-XXXSP
M306V5EESP
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
67
Rev. 1.0
The timing for the DMA request bit to turn to 1 when an external factor is selected synchronizes with
the signal’s edge applicable to the function specified by the DMA request factor selection bit (synchro-
_______
nizes with the trailing edge of the input signal to each INTi pin, for example).
With an external factor selected, the DMA request bit is timed to turn to 0 immediately before data
transfer starts similarly to the state in which an internal factor is selected.
(3) The priorities of channels and DMA transfer timing
If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period
from the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels
concurrently turn to 1. If the channels are active at that moment, DMA0 is given a high priority to start
data transfer. When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU
finishes single bus access, then DMA1 starts data transfer and gives the bus right to the CPU. Figure
2.9.9 illustrates these operations.
An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer
request signals due to external factors concurrently occur.
BCLK
DMA0
DMA1
DMA0
request bit
DMA1
request bit
CPU
INT0
INT1
Obtainm
ent of the
bus right
An example in which DMA transmission is carried out in minimum
cycles at the time when DMA transmission request signals due to
external factors concurrently occur.
Figure 2.9.9 An example of DMA transfer effected by external factors


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn