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M306V5ME-XXXSP Datasheet(PDF) 56 Page - Mitsubishi Electric Semiconductor

Part No. M306V5ME-XXXSP
Description  SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
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Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
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M306V5ME-XXXSP Datasheet(HTML) 56 Page - Mitsubishi Electric Semiconductor

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M306V5ME-XXXSP
M306V5EESP
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
56
Rev. 1.0
2.8 Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog
timer interrupt is generated when an underflow occurs in the watchdog timer. Bit 7 of the watchdog timer
control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). Thus the watchdog
timer’s period can be calculated as given below. The watchdog timer’s period is, however, subject to an
error due to the pre-scaler.
Watchdog timer period =
For example suppose that BCLK runs at 10 MHz and that 16 has been chosen for the dividing ratio of the
pre-scaler, then the watchdog timer’s period becomes approximately 52.4 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Figure 2.8.1 shows the block diagram of the watchdog timer. Figure 2.8.2 shows the watchdog timer control
register and Figure 2.8.3 shows the watchdog timer start register.
pre-scaler dividing ratio (16 or 128) ! watchdog timer count (32768)
BCLK


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