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M306V5ME-XXXSP Datasheet(PDF) 47 Page - Mitsubishi Electric Semiconductor

Part No. M306V5ME-XXXSP
Description  SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
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Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
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M306V5ME-XXXSP Datasheet(HTML) 47 Page - Mitsubishi Electric Semiconductor

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M306V5ME-XXXSP
M306V5EESP
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
47
Rev. 1.0
Interrupt sources without priority levels
7
Value set in the IPL
Watchdog timer
Other
Not changed
0
2.7.12 Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 2.7.6 is set in the IPL.
Table 2.7.6 Relationship between interrupts without interrupt priority levels and IPL
Stack pointer (SP) value
Interrupt vector address
16-Bit bus, without wait
8-Bit bus, without wait
Even
Even
Odd (Note 2)
Odd (Note 2)
Even
Odd
Even
Odd
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
Table 2.7.5 Time required for executing the interrupt sequence
Reset
Indeterminate
1
2
34
56
78
9
10
11
12
13
14
15
16
17
18
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Indeterminate
SP-2
contents
SP-4
contents
vec
contents
vec+2
contents
Interrupt
information
Address
0000
Indeterminate
SP-2
SP-4
vec
vec+2
PC
BCLK
Address bus
Data bus
W
R
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 2.7.5.
________
Notes 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coinci-
dence interrupt or of a single-step interrupt.
2: Locate an interrupt vector address in an even address, if possible.
Figure 2.7.5 Time required for executing the interrupt sequence


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