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IS41LV32256-35TQ Datasheet(PDF) 3 Page - Integrated Silicon Solution, Inc |
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IS41LV32256-35TQ Datasheet(HTML) 3 Page - Integrated Silicon Solution, Inc |
3 / 19 page Integrated Silicon Solution, Inc. 3 Rev. A 09/29/00 IS41LV32256 ISSI® PIN CONFIGURATIONS 100-Pin PQFP, TQFP PIN DESCRIPTIONS A0-A8 Address Inputs RAS Row Address Strobe CAS0 Column Address Strobe for First Byte (I/O0-I/O7) CAS1 Column Address Strobe for Second Byte (I/O8-I/O15) CAS2 Column Address Strobe for Third Byte (I/O16-I/O23) CAS3 Column Address Strobe for Fourth Byte (I/O24-I/O31) WE Write Enable OE Output Enable I/O0-I/O31 Data Inputs/Outputs Vcc +3.3V Supply GND Ground NC No Connection: This pin should be left unconnected or tied to ground. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/O3 Vcc I/O4 I/O5 GND I/O6 I/O7 Vcc I/O16 I/O17 GND I/O18 I/O19 Vcc Vcc GND I/O20 I/O21 GND I/O22 I/O23 Vcc CAS0 CAS2 WE NC NC RAS NC NC I/O28 Vcc I/O27 I/O26 GND I/O25 I/O24 Vcc I/O15 I/O14 GND I/O13 I/O12 Vcc GND Vcc I/O11 I/O10 GND I/O9 I/O8 Vcc NC CAS3 CAS1 NC NC OE NC A8 |
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