7 / 15 page
CY7C4282V
CY7C4292V
7
Notes:
12. The clocks (RCLK, WCLK) can be free-running during reset.
13. For standalone or width expansion configuration only.
14. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
15. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
16. The first word is available the cycle after EF goes HIGH, always.
Switching Waveforms (continued)
Reset Timing
tRS
tRSR
Q0 –Q8
RS
tRSF
tRSF
tRSF
OE=1
OE=0
REN,WEN
EF,PAE
FF,PAF
4282V–8
[12]
[14]
tRSS
LD
[13]
D0 (FIRSTVALID WRITE)
First Data Word Latency after Reset with Simultaneous Read and Write
tSKEW1
WEN
WCLK
Q0 –Q8
EF
REN
OE
tOE
tENS
tOLZ
tDS
RCLK
tREF
tA
tFRL
D1
D2
D3
D4
D0
D1
D0 –D8
4282V–9
tA
[15]
[16]
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
