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CY7C4282V-15ASI Datasheet(PDF) 3 Page - Cypress Semiconductor

Part No. CY7C4282V-15ASI
Description  64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C4282V-15ASI Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY7C4282V
CY7C4292V
3
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
....................................... −65
°C to +150°C
Ambient Temperature with
Power Applied
.................................................... −55
°C to +125°C
Supply Voltage to Ground Potential
..........−0.5V to V
CC +0.5V
DC Voltage Applied to Outputs
in High Z State
..............................................−0.5V to V
CC+0.5V
DC Input Voltage
.........................................−0.5V to V
CC +0.5V
Output Current into Outputs (LOW) ............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Pin Definitions
Signal Name
Description
I/O
Description
D0−8
Data Inputs
I
Data Inputs for 9-bit bus.
Q0−8
Data Outputs
O
Data Outputs for 9-bit bus.
WEN
Write Enable
I
The only write enable when device is configured to have programmable flags. Data is
written on a LOW-to-HIGH transition of WCLK when WEN is asserted and FF is HIGH.
REN
Read Enable
I
Enables the device for Read operation. REN must be asserted LOW to allow a Read
operation.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty.
When LD is LOW, RCLK reads data out of the programmable flag-offset register.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro-
grammed into the FIFO. PAE is synchronized to RCLK.
PAF/XO
Programmable
Almost Full/
Expansion
Output
O
Dual-Mode Pin:
Cascaded - Connected to XI of next device.
Not Cascaded - When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is synchronized to WCLK.
FL/RT
First Load/
Retransmit
I
Dual-Mode Pin:
Cascaded - The first device in the daisy chain will have FL tied to VSS; all other devices
will have FL tied to VCC. In standard mode or width expansion, FL is tied to VSS
on all devices.
Not Cascaded - Retransmit function is available in stand-alone mode by strobing
RT.
XI/LD
Expansion In-
put/Load
I
Dual-Mode Pin:
Cascaded - Connected to XO of previous device.
Not Cascaded - LD is used to write or read the programmable flag offset registers. LD
must be asserted LOW during reset to enable standalone or width expansion operation.
If programmable offset register access is not required, LD can be tied to RS directly.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connect-
ed. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
Operating Range
Range
Ambient
Temperature
VCC
[2]
Commercial
0
°C to +70°C
3.3V
+ /−300mV
Industrial[1]
−40
°C to +85°C
3.3V
+ /−300mV
Notes:
1.
TA is the “instant on” case temperature.
2.
VCC Range for commercial -10 ns is 3.3V ± 150 mV.


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