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CY7C4282V-10ASC Datasheet(PDF) 13 Page - Cypress Semiconductor

Part No. CY7C4282V-10ASC
Description  64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C4282V-10ASC Datasheet(HTML) 13 Page - Cypress Semiconductor

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CY7C4282V
CY7C4292V
13
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred and at least one word has been read since
the last RS cycle. A HIGH pulse on RT resets the internal read
pointer to the first physical location of the FIFO. WCLK and
RCLK may be free running but must be disabled during and
tRTR after the retransmit pulse. With every valid read cycle after
retransmit, previously accessed data is read and the read
pointer is incremented until it is equal to the write pointer. Flags
are governed by the relative locations of the read and write
pointers and are updated during a retransmit cycle. Data writ-
ten to the FIFO after activation of RT are transmitted also. The
full depth of the FIFO can be repeatedly retransmitted.
Width Expansion Configuration
Word width may be increased simply by connecting the corre-
sponding input control signals of multiple devices. A composite
flag should be created for each of the end-point status flags
(EF and FF). The partial status flags (PAE and PAF) can be
detected from any one device. Figure 2 demonstrates a 18-bit
word width by using two CY7C4282V/92V. Any word width can
be attained by adding additional CY7C4282V/92V.
When the CY7C4282V/92V is in a Width Expansion Configu-
ration, the Read Enable (REN) control input can be grounded
(see Figure 2). In this configuration, the Load (LD) pin is set to
LOW at Reset so that the pin operates as a control to load and
read the programmable flag offsets.
Figure 2. Block Diagram of 64Kx9/128Kx9 Low-Voltage Deep Sync FIFO Memory Used in a Width Expansion
Configuration
FF
FF
EF
EF
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
PROGRAMMABLE(PAE)
HALF FULL FLAG (HF)
FULL FLAG (FF)
9
18
DATA IN (D)
RESET (RS)
9
RESET (RS)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAF)
EMPTY FLAG (EF)
9
DATA OUT (Q)
918
FIRST LOAD (FL)
EXPANSION IN (XI)
4282V–17
FIRST LOAD (FL)
EXPANSION IN (XI)
7C4282V
7C4292V
7C4282V
7C4292V


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