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CY7C4282V Datasheet(PDF) 2 Page - Cypress Semiconductor

Part No. CY7C4282V
Description  64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion
Download  15 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C4282V Datasheet(HTML) 2 Page - Cypress Semiconductor

 
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CY7C4282V
CY7C4292V
2
Functional Description (continued)
The CY7C4282V/92V provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost Full.
The Almost Empty/Almost Full flags are programmable to sin-
gle word granularity. The programmable flags default to Emp-
ty+7 and Full
−7.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full, and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle
All configurations are fabricated using an advanced 0.35
µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Pin Configuration
STQFP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
16
4282V–2
CY7C4282V
CY7C4292V
WEN
RS
D8
D7
D6
N/C
N/C
N/C
N/C
N/C
N/C
D5
N/C
D2
D4
D3
Q5
Q4
GND
Q3
Q2
VCC
Q1
Q0
GND
N/C
FF
OE
EF
N/C
GND
FL/RT
Selection Guide
7C4282V/92V-10
7C4282V/92V-15
7C4282V/92V-25
Maximum Frequency (MHz)
100
66.7
40
Maximum Access Time (ns)
8
10
15
Minimum Cycle Time (ns)
10
15
25
Minimum Data or Enable Set-Up (ns)
3.5
4
6
Minimum Data or Enable Hold (ns)
0
0
1
Maximum Flag Delay (ns)
8
10
15
Active Power Supply
Current (ICC) (mA)
Commercial
25
25
25
Industrial
30
CY7C4282V
CY7C4292V
Density
64k x 9
128k x 9
Package
64-pin 10x10 TQFP
64-pin 10x10 TQFP


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