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AD8197 Datasheet(PDF) 28 Page - Analog Devices

Part No. AD8197
Description  4:1 HDMI/DVI Switch with Equalization
Download  32 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD8197 Datasheet(HTML) 28 Page - Analog Devices

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AD8197
Preliminary Technical Data
PrA| Page 28 of 32
These four signals can be switched through the auxiliary bus of
the AD8197 and do not need to be routed with the same strict
considerations as the high speed TMDS signals.
In general, it is sufficient to route each auxiliary signal as a
single-ended trace. These signals are not sensitive to impedance
discontinuities, do not require a reference plane, and can be
routed on multiple layers of the PCB. However, it is best to
follow strict layout practices whenever possible to prevent the
PCB design from affecting the overall application. The specific
routing of the HPD, CEC, and DDC lines depends upon the
application in which the AD8197 is being used.
For example, the maximum speed of signals present on the
auxiliary lines is 100 kHz I2C data on the DDC lines; therefore,
any layout that enables 100 kHz I2C to be passed over the DDC
bus should suffice. The HDMI 1.3 specification, however, places
a strict 50 pF limit on the amount of capacitance that can be
measured on either SDA or SCL at the HDMI input connector.
This 50 pF limit includes the HDMI connector, the PCB, and
whatever capacitance is seen at the input of the AD8197, or an
equivalent receiver. There is a similar limit of 100 pF of input
capacitance for the CEC line.
The parasitic capacitance of traces on a PCB increases with
trace length. To help ensure that a design satisfies the HDMI
specification, the length of the CEC and DDC lines on the PCB
should be made as short as possible. Additionally, if there is a
reference plane in the layer adjacent to the auxiliary traces in
the PCB stack-up, relieving or clearing out this reference plane
immediately under the auxiliary traces significantly decreases
the amount of parasitic trace capacitance. An example of the
board stackup is shown in Figure 33.
PCB DIELECTRIC
LAYER 1: SIGNAL (MICROSTRIP)
SILKSCREEN
SILKSCREEN
PCB DIELECTRIC
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
LAYER 3: PWR (REFERENCE PLANE)
LAYER 4: SIGNAL (MICROSTRIP)
W
3W
3W
REFERENCE LAYER
RELIEVED UNDERNEATH
MICROSTRIP
Figure 33. Example Board Stackup
HPD is a dc signal presented by a sink to a source to indicate
that the source EDID is available for reading. The placement
of this signal is not critical, but it should be routed as directly
as possible.
When the AD8197 is powered up, one set of the auxiliary in-
puts is passively routed to the outputs. In this state, the AD8197
looks like a 100 Ω resistor between the selected auxiliary inputs
and the corresponding outputs as illustrated in Figure 27. The
AD8197 does not buffer the auxiliary signals, therefore, the
input traces, output traces, and the connection through the
AD8197 all must be considered when designing a PCB to meet
HDMI/DVI specifications. The unselected auxiliary inputs of the
AD8197 are placed into a high impedance mode when the device
is powered up. To ensure that all of the auxiliary inputs of the
AD8197 are in a high impedance mode when the device is powered
off, it is necessary to power the AMUXVCC supply as illustrated
in Figure 28.
In contrast to the auxiliary signals, the AD8197 buffers the
TMDS signals, allowing a PCB designer to layout the TMDS
inputs independently of the outputs.


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