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AD7980 Datasheet(PDF) 14 Page - Analog Devices

Part No. AD7980
Description  16-bit, 1 MSPS PulSAR ADC in MSOP/QFN
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7980 Datasheet(HTML) 14 Page - Analog Devices

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AD7980
Preliminary Technical Data
Rev Pr C | Page 14 of 22
CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is usually used when a single AD7980 is connected
to an SPI compatible digital host. The connection diagram is
shown in Figure 15 and the corresponding timing is given in
Figure 16.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it will continue to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When the conversion is complete, the AD7980
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are then clocked by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge will
allow a faster reading rate provided it has an acceptable hold
time. After the 16th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CNV
SCK
SDO
SDI
DATA IN
CLK
CONVERT
VIO
DIGITAL HOST
AD7980
Figure 15. CS Mode 3-Wire, No BUSY Indicator
Connection Diagram (SDI High)
SDO
D15
D14
D13
D1
D0
tDIS
SCK
1
2
3
14
15
16
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
ACQUISITION
SDI = 1
tCNVH
tACQ
tEN
Figure 16. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)


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