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VSC7121 Datasheet(PDF) 2 Page - Vitesse Semiconductor Corporation

Part No. VSC7121
Description  Quad Port Bypass Circuit for 1.0625 Gbit/sec Fibre Channel Arbitrated Loop Disk Arrays
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Maker  VITESSE [Vitesse Semiconductor Corporation]
Homepage  http://www.vitesse.com
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VSC7121 Datasheet(HTML) 2 Page - Vitesse Semiconductor Corporation

 
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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7121
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
Page 2
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
8/31/98
G52110-0, Rev. 4.1
Table 1 is a truth table detailing the data flow through the VSC7121. Figure 1 shows a timing diagram of the
data relationship in the VSC7121. There are no critical timing (setup, hold, or delay) parameters for the
VSC7121 as this part routes the serial data encoded with the baud clock that is extracted by a Fibre Channel
receiver. The primary AC parameter of importance is the jitter or data eye degradation inserted by the port
bypass circuit. The design of the VSC7121 minimizes jitter accumulation by using fully differential circuits.
This provides for symmetric rise and fall delays as well as noise rejection.
Table 1: Truth Table
Figure 1: Timing Waveforms
SELECT STATE
DATA OUTPUTS
SEL1
SEL2
SEL3
SEL4
OUT
SO4
SO3
SO2
SO1
LLLL
IN
IN
IN
IN
IN
L
L
L
H
SI4
IN
IN
IN
IN
L
L
H
L
SI3
SI3
IN
IN
IN
L
H
L
L
SI2
SI2
SI2
IN
IN
H
L
L
L
SI1
SI1
SI1
SI1
IN
HHHH
SI4
SI3
SI2
SI1
IN
T1
T2
Tjitter
OUT+/-
LSO1+/-
LSO2+/-
LSO3+/-
LSO4+/-
IN+/-
LSI1+/-
LSI2+/-
LSI3+/-
LSI4+/-


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