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VSC7121 Datasheet(PDF) 6 Page - Vitesse Semiconductor Corporation

Part No. VSC7121
Description  Quad Port Bypass Circuit for 1.0625 Gbit/sec Fibre Channel Arbitrated Loop Disk Arrays
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Maker  VITESSE [Vitesse Semiconductor Corporation]
Homepage  http://www.vitesse.com
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VSC7121 Datasheet(HTML) 6 Page - Vitesse Semiconductor Corporation

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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7121
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
Page 6
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
8/31/98
G52110-0, Rev. 4.1
Input Structures
Two input structures exists in this part; TTL and High Speed, Differential Inputs. The TTL Inputs will inter-
face with any TTL or 3.3V or 5V CMOS outputs. The High Speed, Differential Inputs are intended to be AC
Coupled per the FC-PH specification. Being AC Coupled, the High Speed, Differential Input buffers are biased
at VDD/2. Refer to Figure 3 for High Speed, Differential Input structure.
Figure 3: High Speed, Differential Inputs (L_SIn/IN)
Because the VSC7121 output buffers are PECL outputs referenced to VDD, the High Speed Differential out-
puts may not be direct coupled to the high speed differential inputs. One example of how to differentially cas-
cade the two VSC7121 is shown in Figure 4. This circuit only applies if trace lengths are less than three inches.
Figure 4: Cascading Two VSC7121
INPUT+
INPUT-
VDD/2
3.3K
3.3K
VDD
GND
0 V
+3.3 V
3.3K
3.3K
VSC7121
OUT+
OUT -
VSC7121
IN+
IN -
VDD
.01
75 Ohm Board/Termination Example
.01


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