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IDT821034 Datasheet(PDF) 6 Page - Integrated Device Technology

Part No. IDT821034
Description  QUAD PCM CODEC WITH PROGRAMMABLE GAIN
Download  19 Pages
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT821034 Datasheet(HTML) 6 Page - Integrated Device Technology

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6
INDUSTRIAL TEMPERATURE RANGE
IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN
corresponding 8-bit Gain Adjustment Registers: MSB GA Register,
which stores the 7 Most Significant bits of gain adjustment coefficient;
and LSB GA Register, which stores the 7 Least Significant bits of
gain adjustment coefficient. All Gain Adjustment Registers start with
‘0’. Gain Adjustment Registers can be accessed by specifying the
channel address (CR.3 and CR.2) in Configuration Register. If
CR[6:4] = ‘100’, CR.0 = ‘1’ and the leading data bit on CI pin is ‘0’ in
a microprocessor write cycle, the 8-bit data on CI pin is latched into
the selected MSB GA Register with MSB first; If CR[6:4] = ‘100’,
CR.0 = ‘0’ and the leading data bit on CI pin is ‘0’ in a microprocessor
write cycle, the 8-bit data on CI pin is latched into the selected LSB
GA Register with MSB first.
All microprocessor cycles are either write cycles or read cycles. In
typical applications, the microprocessor will write control registers as ordered
pairs for CODEC Mode programming (Figure 2), SLIC Mode
programming (Figure 3), or Gain Mode programming (Figure 4). The
first write in the pair is to Configuration Register. This is identified by a
leading ‘1’ on CI pin. If CR.6 = ‘0’ after writing Configuration Register, the
programming is for CODEC mode and the succeeding operation is a
write cycle with a leading ‘0’ on CI pin. The write is intended for the
selected Time Slot Register. The timing diagram for CODEC Mode
programming is shown in Figure 11. If CR.6 = ‘1’ and CR.5 = ‘0’ and
CR.4 = ‘1’ after writing Configuration Register, the programming is for
SLIC control function and the succeeding operation is a read/write cycle.
The write, also with a leading ‘0’ on CI pin, is intended for the selected
SLIC Control Register, while the simultaneous read is from the SLIC
Status Register of the same channel. The timing diagram for SLIC Mode
programming is shown in Figure 10. If CR.6 = ‘1’, CR.5 = ‘0’ and CR.4
= ‘0’ after writing Configuration Register, the programming is for Gain
adjustment function and the succeeding operation is a write cycle with a
leading ‘0’ on CI pin. The write is intended for the selected Gain
Adjustment Register. The timing diagram for Gain Mode programming
is shown in Figure 13.
Configuration Register, Time Slot Registers, SLIC Control Registers and
Gain Adjustment Registers are write only registers while SLIC Status
Registers are read only registers. Refer to Figure 12 for the detail timing
of the Serial Control Interface.
An alternative method of receiving data from SLIC Status Register is
designed for IDT821034. This procedure is initiated when a ‘1111-1110’
command appears on CI. To read from the SLIC Status Registers when
using this method, Configuration Register should be set to indicate the
following operation is a SLIC programming, and then assert a ‘1111-1111’
command on CI. The data from SLIC Status Registers will clock out of CO
pin on CCLK rising edges when CS is low. The timing diagram of this method
is shown in Figure 14. When using this method, CO and CI pins can be
connected together. Either CO or CI will be in high Z state, depending on
the Serial Control Interface is in write cycle or read cycle. When a command
of ‘1111-1101’ appears on CI, the device will terminate this procedure.
Serial
Control
Interface
CO
CI
CS
CCLK
Figure 1. Serial Control Interface Signals
'1' '0' b5
b4
b3 b2 b1
b0
'0' b6 b5
b4
b3 b2 b1
b0
Configuration
Register
Time Slot
Register
Register
Time Slot
Indicator
Register
Indicator
CODEC
Mode
A/
µ-Law
Select
Timing
Mode
Channel
Address
Transmit/Receive
Select
Figure 2. Registers for CODEC Mode Programming
'1'
'1'
'0'
'1'
b3 b2
b1
b0
'0' b6 b5 b4 b3 b2
b1
b0
b7 b6 b5 b4 b3
'0'
'0'
'0'
Configuration
Register
SLIC
Mode
Channel
Address
I/O Configuration
Register
Indicator
SLIC Control
Register
SLIC Status
Register
Register
Indicator
Reserved
Output Data
Image Data
Figure 3. Registers for SLIC Mode Programming
'1' '1'
'0'
'0' b3 b2 b1 b0
'0' b6 b5 b4 b3 b2 b1 b0
Configuration
Register
Gain
Adjustment
Register
Register
7 bits of Gain Adjustment
Indicator
Coefficient
Figure 4. Registers for Gain Mode Programming
Register
Indicator
Gain
Mode
Channel
Address Transmit/
Receive
MSB/LSB


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