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AS4LC4M4883C Datasheet(PDF) 3 Page - Austin Semiconductor

Part No. AS4LC4M4883C
Description  4 MEG x 4 DRAM 3.3V, EDO PAGE MODE
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Manufacturer  AUSTIN [Austin Semiconductor]
Direct Link  http://www.austinsemiconductor.com
Logo AUSTIN - Austin Semiconductor

AS4LC4M4883C Datasheet(HTML) 3 Page - Austin Semiconductor

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AS4LC4M4
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
REFRESH
Preserve correct memory cell data by maintaining power and executing a
?R?A/S cycle (READ, WRITE) or ?R?A/S refresh cycle
(
?R?A/S ONLY, CBR, or HIDDEN) so that all 2,048 combinations of ?R?A/S addresses are executed at least every 32ms, regardless
of sequence. The CBR REFRESH cycle will invoke the refresh counter for automatic
?R?A/S addressing.
,,
,,
V
V
IH
IL
CAS
V
V
IH
IL
RAS
V
V
IH
IL
ADDR
,,
ROW
,,
,
COLUMN (A)
,,
,,,
,
DON’T CARE
UNDEFINED
,
,,
,,
,,
V
V
IH
IL
WE
V
V
IOH
IOL
OPEN
DQ
,
,
,
,,,
,
,,
,,
,,
,,
tWPZ
The DQs go to High-Z if WE falls, and if tWPZ is met,
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
V
V
IH
IL
OE
,
,
VALID DATA (B)
t
WHZ
WE may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
t
WHZ
COLUMN (D)
,,
,,,
,,,
VALID DATA (A)
COLUMN (B)
COLUMN (C)
INPUT DATA (C)
Figure 2
?????W/////E CONTROL OF DQs


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