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AS4LC4M4883C Datasheet(PDF) 1 Page - Austin Semiconductor

Part No. AS4LC4M4883C
Description  4 MEG x 4 DRAM 3.3V, EDO PAGE MODE
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Manufacturer  AUSTIN [Austin Semiconductor]
Direct Link  http://www.austinsemiconductor.com
Logo AUSTIN - Austin Semiconductor

AS4LC4M4883C Datasheet(HTML) 1 Page - Austin Semiconductor

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AS4LC4M4
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
DRAM
AVAILABLE IN MILITARY
SPECIFICATIONS
• MIL-STD-883
• SMD Planned
FEATURES
• Industry-standard x4 pinout, timing, functions and
packages
• High-performance CMOS silicon-gate process
• Single +3.3V
±0.3V power supply
• Low power, 1mW standby; 150mW active, typical
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes:
?R?A/S ONLY, ?C?A/S-BEFORE-?R?A/S (CBR)
HIDDEN
• 2,048-cycle (11 row-, 11 column-addresses)
• Extended Data-Out (EDO) PAGE access cycle
• 5V-tolerant I/Os (5.5V maximum VIH level)
OPTIONS
MARKING
• Timing
60ns access (Contact Factory)
-6
70ns acess
-7
80ns access
-8
• Packages
Ceramic SOJ
ECJ
No. 505
Ceramic LCC
EC
No. 212
Ceramic Gull Wing
ECG
No. 603
PIN ASSIGNMENT (Top View)
24/28-Pin
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
A logic HIGH on
?W/E dictates READ mode while a logic
LOW on
?W/E dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of
?W/E or /C/A/S,
whichever occurs last. An EARLY WRITE occurs when
?W/E is taken LOW prior to /C/A/S falling. A LATE WRITE or
READ-MODIFY-WRITE occurs when
?W/E falls after /C/A/S
was taken LOW. During EARLY WRITE cycles, the data-
outputs (Q) will remain High-Z regardless of the state of
?O/E.DuringLATEWRITEorREAD-MODIFY-WRITEcycles,
?O/E must be taken HIGH to disable the data-outputs prior to
applying input data. If a LATE WRITE or READ-MODIFY-
WRITE is attempted while keeping
?O/E LOW, no write will
occur, and the data-outputs will drive read data from the
accessed location.
The four data inputs and the four data outputs are routed
through four pins using common I/O, and pin direction is
controlled by
?W/E and ?O/E.
FAST PAGE MODE
FAST PAGE operations allow faster data operations
(READ, WRITE or READ-MODIFY-WRITE) within a row-
address-defined page boundary. The FAST PAGE cycle is
always initiated with a row-address strobed-in by
?R?A/S
followed by a column-address strobed-inby
?C?A/S. ?C?A/S may
be toggled-in by holding
?R?A/S LOW and strobing-in differ-
ent column-addresses, thus executing faster memory cycles.
Returning R
?A/S HIGH terminates the FAST PAGE MODE
of operation.
4 MEG x 4 DRAM
3.3V, EDO PAGE MODE
VCC
DQ1
DQ2
/W/E
/R/A/S
NC
A10
A0
A1
A2
A3
VCC
VSS
DQ4
DQ3
/C/A/S
/O/E
A9
A8
A7
A6
A5
A4
Vss
1
2
3
4
5
6
9
10
11
12
13
14
28
27
26
25
24
23
20
19
18
17
16
15
GENERAL DESCRIPTION
The AS4LC4M4 is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x4 con-
figuration. The AS4LC4M4
?R?A/S is used to latch the first 11
bits and
?C?A/S the latter 11 bits. READ and WRITE cycles are
selected with the
?W/E input. A logic HIGH on
?W/E dictates READ mode while a logic LOW on ?W/E dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of
?W/E or ?C?A/S, whichever occurs last. If
?W/E goes LOW prior to ?C?A/S going LOW, the output pins
remain open (High- Z) until the next
?C?A/S cycle, regardless
of
?O/E.
KEY TIMING PARAMETERS
SPEED
tRC
tRAC
tPC
tAA
tCAC
tCAS
-6
110ns
60ns
30ns
30ns
15ns
12ns
-7
130ns
70ns
35ns
35ns
18ns
15ns
-8
150ns
80ns
40ns
40ns
20ns
20ns


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