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PE42612 Datasheet(PDF) 3 Page - Peregrine Semiconductor Corp. |
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PE42612 Datasheet(HTML) 3 Page - Peregrine Semiconductor Corp. |
3 / 4 page Product Brief PE42612 Page 3 of 4 Document No. 70-0217-01 │ www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. Contact sales@psemi.com for full version of datasheet Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Table 5. Truth Table Table 6. Ordering Information Table 4. Pin Descriptions Figure 3. Pin Configuration (Ball-Side Up) Order Code Die ID Description Package Shipping Method PE42612-90 (Unitive) C9817_1 PE42612-DIE-D Film Frame Wafer (Gross Die / Wafer Quantity) PE42612-91 (FCI) C9817_1 PE42612-DIE-D Film Frame Wafer (Gross Die / Wafer Quantity) PE42612-00 C9817_1 PE42612-DIE-1H Evaluation Kit 1 / Box PE42612 Die 7 6 4 5 10 11 1 12 9 2 8 3 GND TX2 GND GND RX1 RX2 V1 VDD V2 N/C ANT TX1 Pin No. Pin Name Description 15 RX1 RF I/O – RX1 2 GND Ground 35 RX2 RF I/O – RX2 4 V1 Switch control input, CMOS logic level 5 V2 Switch control input, CMOS logic level 6 VDD Supply 7 GND Ground 85 TX2 RF I/O - TX2 9 GND Ground 105 TX1 RF I/O - TX1 11 N/C No Connect – Pin to be connected to an electrically isolated low capacitance pad 125 ANT RF Common – Antenna Input Note: 5. Blocking capacitors needed only when non-zero DC voltage present. Path V2 V1 ANT - RX1 0 0 ANT - RX2 0 1 ANT - TX1 1 0 ANT - TX2 1 1 |
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